Vienna Electronics: | DTTF | Global Muon Trigger | Global Trigger |   


FSC - Fast Signal Concentrator Board

FSC card The FSC Card merges the FMM Fast Signals and sends them to the CMS FMM System.

It is constructed as a 6U VME Board with A24/D16 interface on the J1 Connector. It is equipped with two 2mm connectors, but these only provide power, no signal connection is available. The FSC Card is permanently mounted with a VME Extender to be plugged into 9U Crate.

The FSC card's regular place is in the Slot #15 of the Central Backplane, but it can be used in any PHTF Slot.


The FSC Card is equipped with VME Interface. The FSC Board has a fixed VME Offset of "E2h".

The FSC Card contains a Status Register. Its bits 0-3 mirror the Fast Signal output state. The bits 4 and 15 show the state of the internal Change Memory.


All FSC inputs can be masked, in this case these do not participate in generating Fast Signals towards the CMS FMM System.


The FSC receives the FMM signals from DCC directly through the short DCC-FSC Cable. These Contain all four Fast Signals and they are forwarded directly.

The DCC Fast Signals are generated in relation to the DCC Output Memory occupancy. Default value is the Ready state, RDY Signal. The OFW will be sent at 50% FIFO level, the BSY will be sent at 75% FIFO level and OOS will be sent when despite of a Trigger Throttling the FIFO buffer gets full.

TF Boards

The TF Boards generate only two Fast Signals. The OOS will be sent out if the input receiver discovers unsynchronized input data. OFW will be generated when the Derandomizer FIFO of the Local DAQ Block in the TF Boards is over 90% full.

Read back

The FSC card allows to read back the state of the inputs from the 28 bit Indata Register. The lower 24 bits show the status of the TF Wedge inputs (2 bits for every Wedge), while the bits 24-27 show the DCC fast signals line state. As the FSC Board VME data access is 16 bit wide the read back can be achieved by reading the low significant 16 bits from the indata_l Register, the most significant 12 bits from the indata_h Register.


The FSC module allows to mask inputs. As the TF Fast Signals arrive already merged by Wedge there is only a possibility to mask a full Wedge. The masked Wedges are considered as being in state "Ready".

When masking the DCC input only the TF Fast Signals are forwarded. This also means the state "Busy" will never be issued. This masking should never applied when the DAQ system is running, as masking the DCC the Trigger Throttling remains inactive.

The Mask can be applied by writing the 13 bit Mask Vector into the disab_reg. The lowest 12 bits of the Mask Vector contains the mask bits for the Track Finder Boards of the 12 Wedges, the 13th bit masks the DCC Input. Writing "1" into the mask bit disables the input. The default value for the Mask Register is "0", all Inputs enabled.


The Merging of the Fast Signals will be performed following the Priority Scheme. Only one of these Signals can be active at a given time. Thus FSC send out the Fast Signal which has the highest priority among the Inputs. The Priority order is:
  1. RDY - Ready
  2. OFW - Overflow Warning
  3. BSY - Busy
  4. OOS - Out-of-Sync
The masked Inputs are always considered as "RDY".


The Outputs are connected to CMS FMM System. The pinout and signal levels of the DCC Input and the Output are the same, in case of emergency the output cable can be directly connected to the DCC Fast Signal output socket. In this case the TF Boards do not participate in Fast Signal generation.


The FSC Card gives a possibility to put a Test Pattern to its output. The tester should write "1" into the ctrl_test_mode Register and write the 4 bit Test Vector into the test_reg Register. Test Mode should never activated when the DAQ system is running!


The FSC card contains readable Counters that show the actual value of the Orbit Counter (orc_l and orc_h Register pair), the Event Counter (evc_l and oevc_h Register pair) and the BX Counter (bxc Register).

The Event Counter can be reset independently from the TTC system "Reset" or "Resync" signals by writing "1" into the ctrl_evc_res Register. The Orbit Counter can be reset in a similar way by writing "1" into the ctrl_orc_res Register.

Change Memory

The FSC Board contains a set of Change Memories. When any of the input lines change all input line's state will be written into the Change Memory and the memory address pointer is automatically incremented. There are Change Memories for the Input data, the Orbit Counter, the BX Counter and the Event Counter, thus the exact time of the Change will be logged, as well.

All Change Memories are 512 Entry long. When filled up the new data will overwrite the old one, but the bit 4 of the Status register will be set showing the Change Memory overflow. The bit 15 of the Status register shows if the Change Memory is empty. After the first entry this bit will be set to "1". The Memory Pointer of the Change Memory can be reset by writing "1" into the ctrl_mem_pnt_res Register. This also resets the above status bits.


Last modified by János Erö on Aug. 18th, 2010