Quick recipe to simulate and create the GMT chips

1. Check out the code from the CVS repository

Change to the directory under which the GMT structure should be created. The following commands will create a subdirectory 'GMT' containing the whole GMT tree below this directory.

setenv CVSROOT :pserver:user@hepcvs.oeaw.ac.at:/data/cms/cvsroot
cvs login
cvs co -r tagname GMT

user is your user name at hepcvs (ask Gerhard Walzel (gerhard@hephy.oeaw.ac.at) for help if needed).

A valid password is required when logging in to the CVS server.

tagname is the tag (version) of the code and tools to check out. (e.g. GMTBoard_beh_works_14Nov2003)

2. Initialize the environment

eval `GMT/scripts/setup`

(Note that the quotes are backwards quotes.)

This will set up environment variables needed by the scripts and makefiles and some of the tools. The command may be added at the end of the ~/.cshrc file in order to be exected automatically at login to the CERN dsy server.

3. Make the Look-Up-Table Wrapper VHDL and XCO/COE files

Look-up tables are stored as '.lut' files in the /lut subdirectory of a package. The .lut files contain all the information about the LUT (inputs, outputs, contents, block or distributed RAM, VME address width). The make_luts tool is used to create wrapper VHDL code and XCO/COE files for the luts. XCO and COE files are used by the Xilinx Core Generator to generate VHDL and EDN models of the dual port RAMS used for the LUTs (The documentation of the Xilinx Core Generator provides more information on this.).

cd GMT/src
make_luts

The tool will createa '.vhd' wrapper for each '.lut' file as well as a subdirectory for each lut below the directory of the '.lut' file. The subdirectory will contain a subdirectory for each of the TargetFamilies used in the corresponding Package. The .vhd wrappers may be stored in the CVS repository.

Note: the make_luts tool can also be run inside a package or for a single LUT.

4. Elaborate Look-Up-Table cores and other cores

To elaborate all cores execute:

cd GMT/src
redo_cores

This will find all cores and run Xilinx Core Generator to (re-)generate them. The execution may take a while if done for all packages at once (30 min).
5. Simulate a Chip

Change to the chip package test directory and run gmake:

cd GMT/src/LogicFPGA/test
gmake test_lf

or

cd GMT/src/MipISOAU/test
gmake test_miau

6. Simulate the whole GMT Board

cd GMT/src/GMTBoard/test
gmake test_board

7. Synthesize a Chip

The makesyn tool can be used to prepare the environment for running Synplify and the Xilinx implementation tools. makesyn can be run in a package (e.g. /src/LogicFPGA) or in /src to prepare environments for all the chips at once.

cd GMT/src
makesyn

This will create a tree GMT/synth and another tree GMT/xilinx. Synplify project files will be created in the directories GMT/synth/ChipName/Target. Makefiles to run the Xilinx tools will be created in the directories GMT/xilinx/ChipName/Target.

After this step Synplify has to be run manually for each Chip (version 7.33 has been used so far) and for each Target of a chip. Due to license limitations at CERN it is not possible to run Synplify in batch mode. All that has to be done in Synplify is to Open a project file and to hit the 'Run' button. Synplify will store its results in the /rev_1 subdirectory.

Note: makesyn creates a symbolic link form the Xilinx implementation directory to the output edf file of the synthesis.

8. Implement the Design

Change to the corresponding directory in the GMT/xilinx/ tree and run gmake.

cd GMT/xilinx/LogicFPGAbrlchip/XC2V3000-BF957-4/
gmake

The Xilinx implementation tools are run for the chip. The results are stored in the impl/ subdirectory. Depending on the chip this procedure may take between about 1 minute to more than 1 hour.
9. Generate .svf file

cd GMT/xilinx/svf

Make a copy of one of the template .cmd files (containing the entire JTAG chain) and edit it to program the proms of the desired chips

impact -batch [filename.cmd]

Note: the output file name/path is specified in the .cmd file in the following command:

setCable -port svf -file "[path/outfile.svf]"

Note: normally, generated firmware is copied to /afs/cern.ch/cms/TRIDAS/l1global/gmt/firmware/YYYY_MM_DD_CHIPNAME, where CHIPNAME is SRT, AUB, ...