Directory structure

In the following the directory stucture used in the development of the GMT FPGAs from VHDL source is detailed. The structure reflects an attempt to organize the many files produced by the different tools used for simulation, synthesis and implementation. Specifically the structure aims to

separate source files from files that can be generated by tools,
provide a means to develop multiple chips of a common type with possible slight variations,
provide a means to implement chips in different target devices (Virtex2, Spartan3, ...).

The structure shown below has been used to solve the problem at hand. There is still room for improvement but the current solution provides a nice working solution.

GMT/src/Package1/src
                /test
                /lut/XYlut/TargetFamily1
                          /TargetFamily2
                    /ABlut/TargetFamily1
                     ..
                /cores/TargetFamily1
                      /TargetFamily2
                /xaw
                /ucf/Target1
                    /Target2
                     ...
       /Package2/...

GMT/scripts

GMT/doc

GMT/simu_nc/ChipType1
           /ChipType2

GMT/timesim/ChipType1
           /ChipType2

GMT/synth/Chip1/Target1/
               /Target2/

         /Chip2/Target1

GMT/xilinx/Chip1/Target1/
                /Target2/

          /Chip2/Target1

GMT/vhdldoc

The /src tree contains all source files to simulate and synthesize/implement the chips. Besides VHDL sources, the /src tree also contains additioanl files such as constraint files used in the implementation.

The /scripts tree contans scripts and tools used to generate intermediate files and to prepare the environments to run the various tools. The /scripts directory should be included in the search path.

The /doc tree contains documentation on the structure and the tools.

The /src and /scripts and /doc trees are maintained in a CVS repository.

All other trees (/simu_nc, /timesim, /synth, /xilinx, /vhdldoc ) can be generated by running various scripts and tools. They are not stored in CVS.

Packages, ChipTypes, Chips, Targets ...

The /src tree is organized in packages. Packages are used to group source files. Source files are mainly VHDL files but also some related files can be stored in a Package. Usually a package either contains all the source files for a certain type of chip (e.g. the 'InputFPGA' Package) or it contains source files which perform a function that is used in multiple chips (e.g. the 'Common' Package). The 'GMTBoard' package contains a VHDL model of the entire GMT board together with a test bench.

Packages representing a chip type should include all the files necessary to generate the chip.

ChipType is a type of chip (defined in a package) such as InputFPGA or LogicFPGA.

There may be multiple Chips of a certain ChipType (Barrel Logic FPGA, Forward Logic FPGA). These Chips usually differ only in the top level VHDL file which is used to assign the names of the I/O pins and to pass generic parameters to the levels below. All other VHDL files are used in common.

Each Chip can be implemented for multiple Target devices (Different chip sizes, chip packages, speed grades, chip families).

If different TargetFamilies are used (e.g. Virtex2, Spartan3) then some of the cores have to be produced separately for each TargetFamily.

Organization of a package

The /src subdirectory of a Package contains VHDL source files.

The (optional) /test subdirectory contains VHDL test benches, files with test-data and a Makefile to run the Cadence NCSIM tools. After running a test bench, the output file is also stored in the /test directory.

The (optional) /lut subdirectory of a Package contains '.lut' look-up-table description files, vhdl-wrappers generated from the '.lut' files and subdirectories for each LUT containing the files needed by and genearted by teh XIlinx Core generator. The subdirectories for the LUTs are split for the differenct target families (currently Virtex2, Spartan3).

The (optional) /cores directories containes cores generated by Core Generator (e.g. a comparator). The cores have to exist for each of the target device families (Virtex2, Spartan 3).

The (optional) /xaw directory contains VHDL models generated by the Xilinx Architexture Wizard for correctly instantiate the DCMs (Digital CLock Managers).

The /ucf directory contains constraint files for each Chip and each Target device. These files are linked to the corresponding /xilinx/... implementation directory by the makesyn tool.

Hannes Sakulin, $Date: 2005/02/01 15:43:48 $ , $Revision: 1.3 $