eval this file to setup the tools and paths for GMT development.
Syntax:
eval `GMT/scripts/setup`
This script creates a 'lut' wrapper and the '.xco' and '.coe' files for each .lut file in the current directory and below.
A name of a .lut file (or pattern) can be given as an optional argument Use single quotes to pass a pattern (by default *.lut is used).
The VHDL wrapper is created in the same dir as the .lut file.
.xco and .coe files are created in a sub-directory with the same name as the '.lut' file. .xco and .coe files are created separately for each target family as specified in the 'Targets' file of the package.
This script re-elaborates all the cores in and below the directory from where it is called using the coregen project file located in /scripts.
This script makes the Synplify project files for each chip and for each implementation as well as makefiles to run the Xilinx tools.
It creates a tree GMT/synth and another tree GMT/xilinx. Synplify project files are created in the directories GMT/synth/ChipName/Target. Makefiles to run the Xilinx tools are created in the directories GMT/xilinx/ChipName/Target.
This script has to be called inside a package (i.e. GMT/src/LogicFPGA) or in the source dir (GMT/src) in order to create the environments for all chips at once.
This perl script scans the XXXVMEAddrMap.vhd files of the GMT FPGAs and extracts an address table for use in the online software. The script is invoked using the Makefile in the GMT/src directory. Change to the directory and invoke it by the command gmake atable.
There are also makefiles in the GMT/xilinx/Chip/Target directories to run the xilinx tools. Usage: change to the GMT/xilinx/Chip/Target directory and type gmake
A further makefile resides in the GMT/src directory. It is used to extract the address table form teh VHDL and to automatically generate the VHDL reference manual using VHDLDOC. Usage: change to GMT/src and type gmake atable or gmake doc. Note: the makefiles are designed for gmake, not make.