Package Documentation

entity BUFG_DCM_80

BUFG_DCM_80 VHDL submodule.

Used Packages

IEEE.std_logic_1164 all
UNISIM.VCOMPONENTS all

Ports

CLK_IN in std_logic
RST in std_logic
CLK1X out std_logic
CLK2X out std_logic
LOCK out std_logic

Architectures

BUFG_DCM_80_arch

Detailed Description

DCM with CLK0 and CLK2x output and BUFG drivers Device: Virtex-II Family

copied fromXilinX Virtex2 UG -- HS needs 90 us to lock (at 40 MHz -> 4000 clocks) reset needs to be high for at least 3 cycles after reconfig

Generated by: taurokc@dsy-srv3 on Fri Aug 25 11:56:55 2006.