entity BXReadCounter

12 bit BX counter used for the read address in the FIFOs of the Input Chips and Sort Chip. Also used as reference bunch counter in the ROP chip.

More...

Sourcefile...

Used Packages

IEEE.Std_logic_1164 all
IEEE.Numeric_std all
UNISIM.VCOMPONENTS all

Generics

lat_delay_reg_addr integer

Ports

iBCReset in std_logic
iL1A in std_logic
oDo5BX out std_logic
oBXReadCounter out std_logic_vector(11 downto 0)
oL1A_pulse out std_logic
vme_addr in std_logic_vector
vme_data in std_logic_vector
vme_en in std_logic
vme_wr in std_logic
vme_data_out out std_logic_vector(15 downto 0)
vme_en_out out std_logic
clk in std_logic
reset in std_logic

Architectures

behavioral

Detailed Description

Includes the delay from BCReset to reset of counter. (this delay is the same in all GMT chips). Also generates the L1 accept pulse for either 3 or 5 bx (as configured by VME). In 3bx mode, an extra flip-flop is added to the reset delay so that the delay settign does not have to be changed when switching from 3bx to 5bx mode.

The minimum programmable delay (both SRL16 set to 0000) from BCReset to L1A for bunch crossing 0 is 4bx (in 3 bx mode: 2x SRL16 + 1 extra FF + 1 bx read before main bx). (in 5 bx mode: 2x SRL16 + 2 bx read before main bx). The maximum delay between BCReset and L1A for BX 0 (bot SRL set to 1111), is 4+15 = 19 bx.

Version: $Revision: 1.3 $
Date: $Date: 2004/12/17 09:30:37 $
Author: SAKULIN Hannes <hsakulin@dsy-srv5.cern.ch>
Generated: taurokc@dsy-srv3 on Fri Aug 25 11:56:55 2006.