entity InputFPGA

Used Packages

• IEEE.Std_logic_1164 all
• WORK.GMTTypes all
• WORK.ReadOutBufTypes all
• WORK.VMEMux all
• WORK.IFVMEAddrMap all
• virtex2.components all
• UNISIM.VCOMPONENTS all
• IEEE.NUMERIC_STD all

Generics

• input_fpga_idx integer := 0

Ports

• iMuons in TFourInMuons_flat
• oMuonsLF out TFourSyncedMu_flat
• oMuonsAU out TFourSyncedMu_flat
• oPhi out TPhi_vec(0 to 3)
• oEta out TEtaCOU_vec(0 to 3)
• vme_addr in std_logic_vector(19 downto 1)
• vme_data inout std_logic_vector(15 downto 0)
• vme_en in std_logic
• vme_wr in std_logic
• vme_ndtack out std_logic
• vme_nirq out std_logic
• ro_data out std_logic_vector(23 downto 0)
• ro_rdfifo in std_logic
• ro_fetch in std_logic
• l1a in std_logic
• bcreset in std_logic
• l1reset in std_logic
• clk_input in std_logic
• clk_test out std_logic
• clk_out out std_logic
• clk_fb in std_logic
• dcm_locked out std_logic
• reset_dcm in std_logic
• inactive in std_logic
• status out std_logic_vector(1 downto 0)
• test_lemo out std_logic
• test out std_logic_vector(3 downto 0)
• reset_input in std_logic
• dummyb in std_logic

Architectures

• behavioral