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Hierarchy
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Package Documentation
Files
entity InputFPGAbrpc
Input FPGA (BRPC version).
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Sourcefile...
Used Packages
IEEE.Std_logic_1164
all
WORK.GMTTypes
all
WORK.ReadOutBufTypes
all
WORK.VMEMux
all
WORK.IFVMEAddrMap
all
UNISIM.VCOMPONENTS
all
IEEE.NUMERIC_STD
all
Ports
bRPCMu
in TFourInMuons_flat
bRPCMu_LF
out TFourSyncedMu_flat
bRPCMu_AU
out TFourSyncedMu_flat
vme_addr
in std_logic_vector(19 downto 1)
vme_data
inout std_logic_vector(15 downto 0)
vme_en_INB
in std_logic
vme_wr_INB
in std_logic
vme_ndtack_INB
out std_logic
vme_nirq_INB
out std_logic
ro_data_INB
out std_logic_vector(23 downto 0)
ro_rdfifo_INB
in std_logic
ro_fetch_INB
in std_logic
l1a_INB
in std_logic
bcreset_INB
in std_logic
l1reset_INB
in std_logic
clk_INB
in std_logic
clk_test_INB
out std_logic
clk_out_INB
out std_logic
clk_fb_INB
in std_logic
dcm_locked_INB
out std_logic
reset_dcm
in std_logic
inactive
in std_logic
status_INB
out std_logic_vector(1 downto 0)
test_lemo_INB
out std_logic
test_INB
out std_logic_vector(3 downto 0)
reset_INB
in std_logic
test_lemo_clk
out std_logic
dummyb_INB
in std_logic
Architectures
behavioral
Detailed Description
Version
: $Revision: 1.10 $
Date
: $Date: 2004/12/17 11:24:27 $
Author
: SAKULIN Hannes <hsakulin@dsy-srv3.cern.ch>
Generated
: taurokc@dsy-srv3 on Fri Aug 25 11:56:55 2006.