entity InputFPGAcsc

Used Packages

• IEEE.Std_logic_1164 all
• WORK.GMTTypes all
• WORK.ReadOutBufTypes all
• WORK.VMEMux all
• WORK.IFVMEAddrMap all
• UNISIM.VCOMPONENTS all
• IEEE.NUMERIC_STD all

Ports

• CSCMu in TFourInMuons_flat
• CSCMu_LF out TFourSyncedMu_flat
• CSCMu_AU out TFourSyncedMu_flat
• CSCPhiCOU out TPhi_vec(0 to 3)
• CSCEtaCOU out TEtaCOU_vec(0 to 3)
• spare_INC_LFB out std_logic
• vme_addr in std_logic_vector(19 downto 1)
• vme_data inout std_logic_vector(15 downto 0)
• vme_en_INC in std_logic
• vme_wr_INC in std_logic
• vme_ndtack_INC out std_logic
• vme_nirq_INC out std_logic
• ro_data_INC out std_logic_vector(23 downto 0)
• ro_rdfifo_INC in std_logic
• ro_fetch_INC in std_logic
• l1a_INC in std_logic
• bcreset_INC in std_logic
• l1reset_INC in std_logic
• clk_INC in std_logic
• clk_test_INC out std_logic
• clk_out_INC out std_logic
• clk_fb_INC in std_logic
• dcm_locked_INC out std_logic
• reset_dcm in std_logic
• inactive in std_logic
• status_INC out std_logic_vector(1 downto 0)
• test_lemo_INC out std_logic
• test_INC out std_logic_vector(3 downto 0)
• reset_INC in std_logic
• dummyb_INC in std_logic

Architectures

• behavioral