entity InputFPGAdt

Used Packages

• IEEE.Std_logic_1164 all
• WORK.GMTTypes all
• WORK.ReadOutBufTypes all
• WORK.VMEMux all
• WORK.IFVMEAddrMap all
• UNISIM.VCOMPONENTS all
• IEEE.NUMERIC_STD all

Ports

• DTMu in TFourInMuons_flat
• DTMu_LF out TFourSyncedMu_flat
• DTMu_AU out TFourSyncedMu_flat
• DTPhiCOU out TPhi_vec(0 to 3)
• DTEtaCOU out TEtaCOU_vec(0 to 3)
• spare_IND_LFF out std_logic
• vme_addr in std_logic_vector(19 downto 1)
• vme_data inout std_logic_vector(15 downto 0)
• vme_en_IND in std_logic
• vme_wr_IND in std_logic
• vme_ndtack_IND out std_logic
• vme_nirq_IND out std_logic
• ro_data_IND out std_logic_vector(23 downto 0)
• ro_rdfifo_IND in std_logic
• ro_fetch_IND in std_logic
• l1a_IND in std_logic
• bcreset_IND in std_logic
• l1reset_IND in std_logic
• clk_IND in std_logic
• clk_test_IND out std_logic
• clk_out_IND out std_logic
• clk_fb_IND in std_logic
• dcm_locked_IND out std_logic
• reset_dcm in std_logic
• inactive in std_logic
• status_IND out std_logic_vector(1 downto 0)
• test_lemo_IND out std_logic
• test_IND out std_logic_vector(3 downto 0)
• reset_IND in std_logic
• dummyb_IND in std_logic

Architectures

• behavioral