entity InputFPGAfrpc

Used Packages

• IEEE.Std_logic_1164 all
• WORK.GMTTypes all
• WORK.ReadOutBufTypes all
• WORK.VMEMux all
• WORK.IFVMEAddrMap all
• UNISIM.VCOMPONENTS all
• IEEE.NUMERIC_STD all

Ports

• fRPCMu in TFourInMuons_flat
• fRPCMu_LF out TFourSyncedMu_flat
• fRPCMu_AU out TFourSyncedMu_flat
• vme_addr in std_logic_vector(19 downto 1)
• vme_data inout std_logic_vector(15 downto 0)
• vme_en_INF in std_logic
• vme_wr_INF in std_logic
• vme_ndtack_INF out std_logic
• vme_nirq_INF out std_logic
• ro_data_INF out std_logic_vector(23 downto 0)
• ro_rdfifo_INF in std_logic
• ro_fetch_INF in std_logic
• l1a_INF in std_logic
• bcreset_INF in std_logic
• l1reset_INF in std_logic
• clk_INF in std_logic
• clk_test_INF out std_logic
• clk_out_INF out std_logic
• clk_fb_INF in std_logic
• dcm_locked_INF out std_logic
• reset_dcm in std_logic
• inactive in std_logic
• status_INF out std_logic_vector(1 downto 0)
• test_lemo_INF out std_logic
• test_INF out std_logic_vector(3 downto 0)
• reset_INF in std_logic
• dummyb_INF in std_logic

Architectures

• behavioral