entity JTAGController

Simplified version of a ScanPSC100 JTAG controller (by J. Ero).

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Used Packages

IEEE.std_logic_1164 all
IEEE.numeric_std all
IEEE.STD_LOGIC_UNSIGNED ALL

Generics

base_address integer := 0
address_increment integer := 2
addr_high integer := 3
addr_low integer := 1

Ports

oTck out std_logic
oTms0 out std_logic
oTms1 out std_logic
oTdo out std_logic
iTdi0 in std_logic
iTdi1 in std_logic
vme_addr in std_logic_vector(addr_high downto addr_low)
vme_data in std_logic_vector(15 downto 0)
vme_en in std_logic
vme_wr in std_logic
vme_dtack out std_logic
vme_data_out out std_logic_vector(15 downto 0)
vme_en_out out std_logic
clk in std_logic
reset in std_logic

Architectures

behavioral

Detailed Description

JTAG Controller that supports two JTAG chains.

The controller is accessed through 8 registers mapped into VME address space. Except for a few minor exception these registers are the same as for the National Semiconductor ScanPSC100F Chip.

The controller's JTAG ports should be connected directly to the I/O pins of the FPGA without any flip-flops in between.

Furthermore the controller needs the 40 MHz clock and a reset signal which has to be asserted at startup to initalize the controller.

Important Note on the VME Interface: The JTAG controller uses a simplified VME interface. vme_en is used as a strobe. It has to be active until vme_dtack ends the cycle. While vme_en is active, bot the addresses and data (for a write) have to be valid. vme_en must change synchronously to the 40 MHz clock (no asynchronous clear) as the falling edge of vme_en is used to trigger actions. ) vme_wr has to be valid and stable duing the whole cycle and for two clocks after the vme_en goes to low.

Main differences to ScanPSC100:

no double buffering
no loopback or other test commands
no running of the JTAG clock without shifting data on TDO or TMS
when shifting, both tdi and tdo have to be enabled. All data shifted in has to be read out subsequently.

Generics:

base_address	VME base address in bytes
address_increment	address increment bewteen successive registers in bytes (2 for word access, 4 for long word access)
addr_high	upper index of vme_addr vector
addr_low	lower index of vme_addr vector (1 for word access, 2 for long word access)

Ports:

oTck	JTAG clock output
oTms0	TMS output for chain 0
oTms1	TMS output for chain 1
oTdo	TDO output (bot chains)
iTdi0	TDI input for chain 0
iTdi1	TDI inout for chain 1
vme_addr	VME adresses (range defined by generics)
vme_data	VME data from VME bus
vme_en	VME enable strobe (see text above)
vme_wr	VME write (see text above)
vme_dtack	VME dtack (see text above)
vme_data_out	VME data to VME bus (16 bit but only lower 8 bits are used)
vme_en_out	VME enabled and one of the registers was addressed. used to multiplex vme_data_out from multiple registers.
clk	40 MHz clock
reset	asynchronous reset, active high (to be asserted at startup)

See also: ScanPSC100F, documentation(http://www.national.com/ds/SC/SCANPSC100F.pdf)

Version: $Revision: 1.11 $
Date: $Date: 2004/12/16 18:58:56 $
Author: SAKULIN Hannes <hsakulin@dsy-srv3.cern.ch>
Generated: taurokc@dsy-srv3 on Fri Aug 25 11:56:55 2006.