Package Documentation

entity LFOvlDisableHotUnit

Calculate disable hot bits from phi and eta of the DT/CSC muons from the other chip/chain.

Used Packages

IEEE.Std_logic_1164 all
IEEE.Numeric_Std all
WORK.GMTTypes all
WORK.LFTypes all
work.LFVMEAddrMap all
work.LFTiming all
work.VMEMux all

Generics

logic_fpga_idx integer := 0

Ports

iPhi in TPhi_vec(0 to 3)
iEta in TEtaCOU_vec(0 to 3)
oDisableHot out std_logic_vector(0 to 3)
oEta4_nr out TEta4_vec(0 to 3)
vme_addr in std_logic_vector
vme_data in std_logic_vector
vme_en in std_logic
vme_wr in std_logic
vme_data_out out std_logic_vector(15 downto 0)
vme_en_out out std_logic
clk in std_logic
sinit in std_logic

Architectures

behavioral

Detailed Description

This LUT has to match the disabled regions in the SortRankEtaPhiLUT in the other Logic FPGA.

Additionally, this unit converts eta from 6 to 4 bits

Version: $Revision: 1.3 $
Date: $Date: 2005/01/31 15:17:29 $
Author: SAKULIN Hannes <hsakulin@dsy-srv3.cern.ch>
Generated: taurokc@dsy-srv3 on Fri Aug 25 11:56:55 2006.