entity LogicFPGA

Logic FPGA (the whole chip).

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Used Packages

IEEE.Std_logic_1164 all
WORK.LFTypes all
WORK.GMTTypes all
WORK.LFTiming all
work.VMEMux all
work.LFVMEAddrMap all
UNISIM.VCOMPONENTS all
IEEE.NUMERIC_STD all

Generics

logic_fpga_idx integer := 0

Ports

iRPCmuons in TFourSyncedMu_flat
iDTCSCmuons in TFourSyncedMu_flat
iPhiCOU in TPhi_vec(0 to 3)
iEtaCOU in TEtaCOU_vec(0 to 3

Architectures

behavioral

Detailed Description

Revision 1.18: feedabe1 24nov2005 LFF to get bad bit 42 via bit 100 from INF Revision 1.19: feed0001 30nov2005 LFB to send bad bit 56 via bit 104 to Sorter

Version: $Revision: 1.18 $
Date: $Date: 2005/12/06 16:11:56 $
Author: SAKULIN Hannes <hsakulin@dsy-srv3.cern.ch>, Updated: A.Taurok
Generated: taurokc@dsy-srv3 on Fri Aug 25 11:56:55 2006.