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entity LogicFPGAbrlchip
Logic FPGA (the whole chip) barrel version.
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Sourcefile...
Used Packages
IEEE.Std_logic_1164
all
WORK.LFTypes
all
WORK.GMTTypes
all
WORK.LFTiming
all
UNISIM.VCOMPONENTS
all
Ports
bRPCmu_LF
in TFourSyncedMu_flat
DTmu_LF
in TFourSyncedMu_flat
CSCPhiCOU
in TPhi_vec(0 to 3)
CSCEtaCOU
in TEtaCOU_vec(0 to 3)
spare_INC_LFB
in std_logic
Architectures
behavioral
Detailed Description
Version
: $Revision: 1.11 $
Date
: $Date: 2004/12/16 18:45:45 $
Author
: SAKULIN Hannes <hsakulin@dsy-srv3.cern.ch>
Generated
: taurokc@dsy-srv3 on Fri Aug 25 11:56:55 2006.