Index
Annotated List
Hierarchy
Deep Hierarchy
Package Documentation
Files
entity MIAUSimuLogic
Simulation Logic in the MipIsoAU Chip.
More...
Sourcefile...
Used Packages
IEEE.Std_logic_1164
all
IEEE.Numeric_std
all
work.VMEMux
all
UNISIM.VCOMPONENTS
all
Generics
simuspyconfig_reg_addr
integer
spydepth_reg_addr
integer
spyarmpulse_reg_addr
integer
spydone_reg_addr
integer
simuspyram_vme_base_address
integer
Ports
iPreBCRes
in std_logic
iBCRes
in std_logic
oData
out std_logic_vector (15 downto 0)
oSimuMode
out std_logic
oDummyIsBCReset
out std_logic
vme_addr
in std_logic_vector
vme_data
in std_logic_vector
vme_en
in std_logic
vme_wr
in std_logic
vme_data_out
out std_logic_vector(15 downto 0)
vme_en_out
out std_logic
clk
in std_logic
reset
in std_logic
Architectures
behavioral
Detailed Description
Version
: $Revision: 1.3 $
Date
: $Date: 2005/02/01 19:05:00 $
Author
: SAKULIN Hannes <hsakulin@dsy-srv5.cern.ch>
Generated
: taurokc@dsy-srv3 on Fri Aug 25 11:56:55 2006.