Index
Annotated List
Hierarchy
Deep Hierarchy
Package Documentation
Files
entity ROPChip
Combined ROP, VME and JTAG Controller Chip for GMT.
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Used Packages
IEEE.Std_logic_1164
all
IEEE.NUMERIC_STD
all
work.VMEMux
all
work.ROPVMEAddrMap
all
Ports
vme_addr
in std_logic_vector(23 downto 1)
vme_data
inout std_logic_vector(15 downto 0)
BERR_EXT
out std_logic
DTACK_EXT
out std_logic
IRQ_X
out std_logic
SINGLE_ACCESS
in std_logic
BLT_ACCESS
in std_logic
DSPULS
in std_logic
DSCYC
in std_logic
DSSYNC
in std_logic
WRITE_I
in std_logic
RESET_MODE
in std_logic
D08_O
in std_logic
D08_E
in std_logic
D16_EO
in std_logic
ASCYC
in std_logic
ASSYNC
in std_logic
ASPULS
in std_logic
SET_RUNNING
out std_logic
VME_LED
out std_logic
dcm_locked_LED
out std_logic
error_LED
out std_logic
vme_en_INF
out std_logic
vme_wr_INF
out std_logic
vme_ndtack_INF
in std_logic
vme_nirq_INF
in std_logic
vme_en_INC
out std_logic
vme_wr_INC
out std_logic
vme_ndtack_INC
in std_logic
vme_nirq_INC
in std_logic
vme_en_IND
out std_logic
vme_wr_IND
out std_logic
vme_ndtack_IND
in std_logic
vme_nirq_IND
in std_logic
vme_en_INB
out std_logic
vme_wr_INB
out std_logic
vme_ndtack_INB
in std_logic
vme_nirq_INB
in std_logic
vme_en_AUF
out std_logic
vme_wr_AUF
out std_logic
vme_ndtack_AUF
in std_logic
vme_nirq_AUF
in std_logic
vme_en_LFF
out std_logic
vme_wr_LFF
out std_logic
vme_ndtack_LFF
in std_logic
vme_nirq_LFF
in std_logic
vme_en_LFB
out std_logic
vme_wr_LFB
out std_logic
vme_ndtack_LFB
in std_logic
vme_nirq_LFB
in std_logic
vme_en_AUB
out std_logic
vme_wr_AUB
out std_logic
vme_ndtack_AUB
in std_logic
vme_nirq_AUB
in std_logic
vme_en_SRT
out std_logic
vme_wr_SRT
out std_logic
vme_ndtack_SRT
in std_logic
vme_nirq_SRT
in std_logic
dcm_locked_INF
in std_logic
dcm_locked_INC
in std_logic
dcm_locked_IND
in std_logic
dcm_locked_INB
in std_logic
dcm_locked_AUF
in std_logic
dcm_locked_LFF
in std_logic
dcm_locked_LFB
in std_logic
dcm_locked_AUB
in std_logic
dcm_locked_SRT
in std_logic
dummy_INF
out std_logic
dummy_INC
out std_logic
dummy_IND
out std_logic
dummy_INB
out std_logic
dummy_AUF
out std_logic
dummy_LFF
out std_logic
dummy_LFB
out std_logic
dummy_AUB
out std_logic
dummy_SRT
out std_logic
status_INF
in std_logic_vector(1 downto 0)
status_INC
in std_logic_vector(1 downto 0)
status_IND
in std_logic_vector(1 downto 0)
status_INB
in std_logic_vector(1 downto 0)
status_AUF
in std_logic_vector(1 downto 0)
status_LFF
in std_logic_vector(1 downto 0)
status_LFB
in std_logic_vector(1 downto 0)
status_AUB
in std_logic_vector(1 downto 0)
status_SRT
in std_logic_vector(1 downto 0)
STAT_GMT
out std_logic_vector(3 downto 0)
reset_INF
out std_logic
reset_INC
out std_logic
reset_IND
out std_logic
reset_INB
out std_logic
reset_AUF
out std_logic
reset_LFF
out std_logic
reset_LFB
out std_logic
reset_AUB
out std_logic
reset_SRT
out std_logic
reset_dcm_INF
out std_logic
reset_dcm_INC
out std_logic
reset_dcm_IND
out std_logic
reset_dcm_INB
out std_logic
reset_dcm_AUF
out std_logic
reset_dcm_LFF
out std_logic
reset_dcm_LFB
out std_logic
reset_dcm_AUB
out std_logic
reset_dcm_SRT
out std_logic
v_nprog_INF
out std_logic
v_cclk_INF
out std_logic
v_din_INF
out std_logic
v_ninit_INF
inout std_logic
v_done_INF
in std_logic
v_nprog_INC
out std_logic
v_cclk_INC
out std_logic
v_din_INC
out std_logic
v_ninit_INC
inout std_logic
v_done_INC
in std_logic
v_nprog_IND
out std_logic
v_cclk_IND
out std_logic
v_din_IND
out std_logic
v_ninit_IND
inout std_logic
v_done_IND
in std_logic
v_nprog_INB
out std_logic
v_cclk_INB
out std_logic
v_din_INB
out std_logic
v_ninit_INB
inout std_logic
v_done_INB
in std_logic
v_nprog_AUF
out std_logic
v_cclk_AUF
out std_logic
v_din_AUF
out std_logic
v_ninit_AUF
inout std_logic
v_done_AUF
in std_logic
v_nprog_LFF
out std_logic
v_cclk_LFF
out std_logic
v_din_LFF
out std_logic
v_ninit_LFF
inout std_logic
v_done_LFF
in std_logic
v_nprog_LFB
out std_logic
v_cclk_LFB
out std_logic
v_din_LFB
out std_logic
v_ninit_LFB
inout std_logic
v_done_LFB
in std_logic
v_nprog_AUB
out std_logic
v_cclk_AUB
out std_logic
v_din_AUB
out std_logic
v_ninit_AUB
inout std_logic
v_done_AUB
in std_logic
v_nprog_SRT
out std_logic
v_cclk_SRT
out std_logic
v_din_SRT
out std_logic
v_ninit_SRT
inout std_logic
v_done_SRT
in std_logic
V_TD_VME2GMT
out std_logic
V_TD_GMT2VME
in std_logic
V_TMS
out std_logic
V_TCK
out std_logic
VA_TD_VME2GMT
out std_logic
VA_TD_GMT2VME
in std_logic
VA_TMS
out std_logic
VA_TCK
out std_logic
ro_data_INF
in std_logic_vector(23 downto 0)
ro_rdfifo_INF
out std_logic
ro_fetch_INF
out std_logic
ro_data_INC
in std_logic_vector(23 downto 0)
ro_rdfifo_INC
out std_logic
ro_fetch_INC
out std_logic
ro_data_IND
in std_logic_vector(23 downto 0)
ro_rdfifo_IND
out std_logic
ro_fetch_IND
out std_logic
ro_data_INB
in std_logic_vector(23 downto 0)
ro_rdfifo_INB
out std_logic
ro_fetch_INB
out std_logic
ro_data_SRT
in std_logic_vector(23 downto 0)
ro_rdfifo_SRT
out std_logic
ro_fetch_SRT
out std_logic
ch_link1
out std_logic_vector(27 downto 0)
ch_link1_clk
out std_logic
en_link1
out std_logic
ch_link2
out std_logic_vector(27 downto 0)
ch_link2_clk
out std_logic
en_link2
out std_logic
l1a_ROP
in std_logic
bcreset_ROP
in std_logic
l1reset_ROP
in std_logic
ro_bus
in std_logic_vector(11 downto 0)
ro_strobe
in std_logic_vector(2 downto 0)
ro_rdrqst
in std_logic
clk_ROP
in std_logic
clk_test_ROP
out std_logic
clk_out_ROP
out std_logic
clk_fb_ROP
in std_logic
inactive
in std_logic
dummyb_ROP
out std_logic
test_pins
out std_logic_vector(7 downto 0)
Architectures
behavioral
Detailed Description
Version
: $Revision: 1.18 $
Date
: $Date: 2006/04/10 09:39:59 $
Author
: SAKULIN Hannes <hsakulin@dsy-srv3.cern.ch>
Generated
: taurokc@dsy-srv3 on Fri Aug 25 11:56:55 2006.