Index
Annotated List
Hierarchy
Deep Hierarchy
Package Documentation
Files
entity ReadOutLogic
Readout logic that goes into the Input or Sort FPGA.
More...
Sourcefile...
Used Packages
IEEE.Std_logic_1164
all
IEEE.Numeric_std
all
work.ReadOutBufTypes
all
UNISIM.VCOMPONENTS
all
Generics
nwords
integer := 4
lat_delay_reg_addr
integer
Ports
data
in TReadoutData_vec(0 to nwords-1)
mondata
in TReadoutMonData_vec(0 to 2
iBXCount
in std_logic_vector(11 downto 0)
iBCReset
in std_logic
iL1A
in std_logic
iL1Reset
in std_logic
vme_addr
in std_logic_vector
vme_data
in std_logic_vector
vme_en
in std_logic
vme_wr
in std_logic
vme_data_out
out std_logic_vector(15 downto 0)
vme_en_out
out std_logic
ro_data
out std_logic_vector(23 downto 0)
ro_rdfifo
in std_logic
ro_fetch
in std_logic
clk
in std_logic
reset
in std_logic
Architectures
behavioral
Detailed Description
Version
: $Revision: 1.5 $
Date
: $Date: 2004/12/17 09:30:38 $
Author
: SAKULIN Hannes <hsakulin@dsy-srv5.cern.ch>
Generated
: taurokc@dsy-srv3 on Fri Aug 25 11:56:55 2006.