entity SortFPGA

Used Packages

• IEEE.Std_logic_1164 all
• WORK.GMTTypes all
• WORK.ReadOutBufTypes all
• WORK.VMEMux all
• WORK.SFVMEAddrMap all
• IEEE.NUMERIC_STD all

Ports

• SortRanks_brl in TSortRank_vector(0 to 3)
• SortRanks_fwd in TSortRank_vector(0 to 3)
• OutMuons_brl in TFourGMTMu_flat
• OutMuons_fwd in TFourGMTMu_flat
• IdxBits_brl in TIndexBits_vector(0 to 3)
• IdxBits_fwd in TIndexBits_vector(0 to 3)
• IsRPCMu_brl in std_logic_vector (0 to 3)
• IsRPCMu_fwd in std_logic_vector (0 to 3)
• Muon12 out std_logic_vector(29 downto 0)
• Muon34 out std_logic_vector(29 downto 0)
• vme_addr in std_logic_vector(19 downto 1)
• vme_data inout std_logic_vector(15 downto 0)
• vme_en_SRT in std_logic
• vme_wr_SRT in std_logic
• vme_ndtack_SRT out std_logic
• vme_nirq_SRT out std_logic
• ro_data_SRT out std_logic_vector(23 downto 0)
• ro_rdfifo_SRT in std_logic
• ro_fetch_SRT in std_logic
• l1a_SRT in std_logic
• bcreset_SRT in std_logic
• l1reset_SRT in std_logic
• clk_SRT in std_logic
• clk_test_SRT out std_logic
• clk_out_SRT out std_logic
• clk_fb_SRT in std_logic
• dcm_locked_SRT out std_logic
• reset_dcm in std_logic
• inactive in std_logic
• reset_SRT in std_logic
• status_SRT out std_logic_vector(1 downto 0)
• test_SRT out std_logic_vector(3 downto 0)
• dummyb in std_logic

Architectures

• behavioral