Package Documentation

entity StartupDCM80Virtex2

Startup block and DCM with 80MHz clock for Virtex2.

Used Packages

IEEE.Std_logic_1164 all
virtex2.components all
UNISIM.VCOMPONENTS all
IEEE.NUMERIC_STD all

Ports

iResetToGSR in std_logic
iTristateToGTS in std_logic
oResetNet out std_logic
iClkFromPAD in std_logic
oClkNet out std_logic
oClk80 out std_logic
iResetDCM in std_logic
oDCMLocked out std_logic

Architectures

behavioral

Detailed Description

Version: $Revision: 1.1 $
Date: $Date: 2006/06/02 09:29:39 $
Author: TAUROK Anton <taurokc@dsy-srv3.cern.ch>
Generated: taurokc@dsy-srv3 on Fri Aug 25 11:56:55 2006.