Package Documentation

entity VMEReadOnlyReg

16 bit VME read-only register.

Used Packages

IEEE.Std_logic_1164 all
IEEE.Numeric_Std all

Generics

init_val std_logic_vector(15 downto 0)
my_vme_base_address integer := 0

Ports

vme_addr in std_logic_vector
vme_en in std_logic
vme_wr in std_logic
vme_data_out out std_logic_vector
vme_en_out out std_logic
vme_clk in std_logic
reset in std_logic

Architectures

behavioral

Detailed Description

Always contains data that is loaded at initilaization (reset) time generates vme_en_out, only if read

Version: $Revision: 1.3 $
Date: $Date: 2005/12/06 16:11:56 $
Author: SAKULIN Hannes <hsakulin@dsy-srv2.cern.ch>
Generated: taurokc@dsy-srv3 on Fri Aug 25 11:56:55 2006.