Package Documentation

entity VMEStatusReg

16 bit VME status register (read only).

Used Packages

IEEE.Std_logic_1164 all
IEEE.Numeric_Std all

Generics

my_vme_base_address integer := 0

Ports

data in std_logic_vector(15 downto 0)
vme_addr in std_logic_vector
vme_en in std_logic
vme_wr in std_logic
vme_data_out out std_logic_vector
vme_en_out out std_logic
vme_clk in std_logic
reset in std_logic

Architectures

behavioral

Detailed Description

always contains data that is input at data port

Version: $Revision: 1.5 $
Date: $Date: 2005/01/20 14:41:42 $
Author: SAKULIN Hannes <hsakulin@dsy-srv2.cern.ch>
Generated: taurokc@dsy-srv3 on Fri Aug 25 11:56:55 2006.