entity VMEWritePulseReg

Used Packages

• IEEE.Std_logic_1164 all
• IEEE.Numeric_Std all

Generics

• my_vme_base_address integer := 0

Ports

• data_pulse out std_logic_vector(15 downto 0)
• vme_addr in std_logic_vector
• vme_data in std_logic_vector
• vme_en in std_logic
• vme_wr in std_logic
• vme_data_out out std_logic_vector
• vme_en_out out std_logic
• vme_clk in std_logic
• reset in std_logic

Architectures

• behavioral