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entity VMEWritePulseReg
16 bit VME Write Pulse register generates 25 ns pulses when written to.
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Used Packages
IEEE.Std_logic_1164
all
IEEE.Numeric_Std
all
Generics
my_vme_base_address
integer := 0
Ports
data_pulse
out std_logic_vector(15 downto 0)
vme_addr
in std_logic_vector
vme_data
in std_logic_vector
vme_en
in std_logic
vme_wr
in std_logic
vme_data_out
out std_logic_vector
vme_en_out
out std_logic
vme_clk
in std_logic
reset
in std_logic
Architectures
behavioral
Detailed Description
Version
: $Revision: 1.2 $
Date
: $Date: 2005/01/20 11:01:47 $
Author
: SAKULIN Hannes <hsakulin@dsy-srv2.cern.ch>
Generated
: taurokc@dsy-srv3 on Fri Aug 25 11:56:55 2006.