--******************************************************************************
--* @short   12-bit Error counter: counts errors and can be read out via VME
--*
--*          Upon a bcreset the counter content is shifted to a register
--*          and the counter is reset.
--*
--*          The value read by VEM always is the count that was counted in the
--*          last orbit.
--******************************************************************************
--* @author  SAKULIN Hannes  <hsakulin@dsy-srv2.cern.ch>
--* @version $Revision: 1.1 $
--* @date    $Date: 2005/01/10 16:30:16 $x
--******************************************************************************
--/
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity ErrorCounter is
  generic (
    my_vme_base_address : integer := 0); -- VME address of this instance

  port (
    -- data port
    count_enable : in    std_logic;
    
    bc_reset     : in    std_logic;
    
    -- VME port
    vme_addr     : in    std_logic_vector;  -- leave unconstrained 
    vme_en       : in    std_logic;
    vme_wr       : in    std_logic;
    vme_data_out : out   std_logic_vector;                                    
    vme_en_out   : out   std_logic;


    
    clk          : in    std_logic;
    reset        : in    std_logic);

end ErrorCounter;


-------------------------------------------------------------------------------
-- Implementation
-------------------------------------------------------------------------------

architecture behavioral of ErrorCounter is

  signal vme_en_out_i     : std_logic;
--   signal vme_en_out_d     : std_logic;
--   signal vme_en_out_pulse : std_logic;

  signal count : std_logic_vector(11 downto 0);

  signal count_register : std_logic_vector(15 downto 0);
  
begin  -- behavioral

  -----------------------------------------------------------------------------
  --*  the counter
  -----------------------------------------------------------------------------
  
  counter: process (clk, reset) is
  begin  -- process counter
    if reset = '1' then
      count <= (others => '0');
--      count_full_i <= '0';
    elsif clk'event and clk = '1' then  -- rising clock edge
      if bc_reset = '1' then
        count <= (others => '0');
      else
        
        if count_enable = '1' then
          count <= std_logic_vector(to_unsigned(to_integer(unsigned(count))+1,12));
        end if;
        
      end if;
      
--       if count = "1111111111111111" then
--         count_full_i <= '1';
--       else
--         count_full_i <= '0';
--       end if;
      
    end if;
  end process counter;

  -----------------------------------------------------------------------------
  --* save the counter upon bc reset
  -----------------------------------------------------------------------------
  
  save_count: process (clk, reset) is
  begin  -- process save_count
    if reset = '1' then
      count_register <= ( others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      if bc_reset = '1' then
         count_register(11 downto 0) <= count;
      end if;  
    end if;
  end process save_count;

  -----------------------------------------------------------------------------
  --* the VME Register
  -----------------------------------------------------------------------------
  error_reg: entity work.VMEStatusReg
    generic map (
      my_vme_base_address => my_vme_base_address)
    port map (
      data         => count_register,
      vme_addr     => vme_addr,
      vme_en       => vme_en,
      vme_wr       => vme_wr,
      vme_data_out => vme_data_out,
      vme_en_out   => vme_en_out_i,
      vme_clk      => clk,
      reset        => reset);


  vme_en_out <= vme_en_out_i;


  
end behavioral;