--******************************************************************************
--* @short   A 32bit block in the readout unit
--*
--*          it contains a 512b deep ring buffer and a 1k derandomizing buffer
--******************************************************************************
--* @author  SAKULIN Hannes  <hsakulin@dsy-srv5.cern.ch>
--* @date    $Date: 2004/12/17 09:30:38 $
--* @version $Revision: 1.3 $
--******************************************************************************
--/
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_std.all;

entity ROPBlock32 is

  port (
    data : in std_logic_vector(31 downto 0);

    wr_addr : in std_logic_vector(8 downto 0);
    rd_addr : in std_logic_vector(8 downto 0);
    we_fifo : in std_logic;

    rd_fifo : in std_logic;

    -- output are two 16-bit registers
    dout_low  : out std_logic_vector(15 downto 0);
    dout_high : out std_logic_vector(15 downto 0);

    clk        : in std_logic;
    sinit_fifo : in std_logic
    );

end entity ROPBlock32;


architecture behavioral of ROPBlock32 is

  component ringbuf512x32
    port (
      addra : in  std_logic_vector(8 downto 0);
      addrb : in  std_logic_vector(8 downto 0);
      clka  : in  std_logic;
      clkb  : in  std_logic;
      dina  : in  std_logic_vector(31 downto 0);
      doutb : out std_logic_vector(31 downto 0);
      wea   : in  std_logic);
  end component;

  component fifo1kx32
    port (
      clk   : in  std_logic;
      sinit : in  std_logic;
      din   : in  std_logic_vector(31 downto 0);
      wr_en : in  std_logic;
      rd_en : in  std_logic;
      dout  : out std_logic_vector(31 downto 0);
      full  : out std_logic;
      empty : out std_logic);
  end component;

-- Synplicity black box declaration
  attribute syn_black_box                  : boolean;
  attribute syn_black_box of ringbuf512x32 : component is true;
  attribute syn_black_box of fifo1kx32     : component is true;

  signal data_to_fifo : std_logic_vector(31 downto 0);
  signal data_from_fifo : std_logic_vector(31 downto 0);
  signal wea_ringbuf : std_logic;

  signal full, empty : std_logic;

begin  -- architecture behavioral

  -- always write into ringbuf
  wea_ringbuf <= '1';

  ringbuf : ringbuf512x32
    port map (
      addra => wr_addr,
      addrb => rd_addr,
      clka  => clk,
      clkb  => clk,
      dina  => data,
      doutb => data_to_fifo,
      wea   => wea_ringbuf);

  fifo : fifo1kx32
    port map (
      clk   => clk,
      sinit => sinit_fifo,
      din   => data_to_fifo,
      wr_en => we_fifo,
      rd_en => rd_fifo,
      dout => data_from_fifo,
      full => full,
      empty => empty);

  dout_low  <= data_from_fifo(15 downto 0);
  dout_high <= data_from_fifo(31 downto 16);
  
end architecture behavioral;