--******************************************************************************
--* @short   Startup block and DCM with 80MHz clock for Virtex2
--******************************************************************************
--* @author  TAUROK Anton  <taurokc@dsy-srv3.cern.ch>
--* @date    $Date: 2006/06/02 09:29:39 $
--* @version $Revision: 1.1 $
--******************************************************************************
--/
library IEEE;
use IEEE.Std_logic_1164.all;

-- need synplify virtex2 library for STARTUP_VIRTEX2
library virtex2;
use virtex2.components.all;

-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.all;
-- pragma translate_on
use IEEE.NUMERIC_STD.all;


entity StartupDCM80Virtex2 is
  port (
    iResetToGSR     : in std_logic;
    iTristateToGTS  : in std_logic;

    oResetNet       : out std_logic;

    iClkFromPAD     : in std_logic;
    oClkNet         : out std_logic;
    oClk80          : out std_logic;
    iResetDCM       : in std_logic;
    oDCMLocked      : out std_logic);
end;


architecture behavioral of StartupDCM80Virtex2 is

  component IBUFG
    port (O : out std_ulogic;
          I : in  std_ulogic);
  end component;

  component ROC
-- synthesis translate_off
    generic (WIDTH :     time       := 100 ns);
-- synthesis translate_on
    port (O        : out std_ulogic := '1');
  end component;

  signal clk_frombuf : std_logic;
  signal clk, clk80         : std_logic;
--  signal roc_reset   : std_logic;
  signal dcm_locked  : std_logic;
begin
  -------------------------------------------------------------------------------
  -- Digital Clock Management
  -------------------------------------------------------------------------------

  Clock_IBUFG : IBUFG                   -- reduces time from PAD to DCM
  port map (O => clk_frombuf,
            I => iClkFromPAD);

  -- DCM with internal feedback and buffer
  theDCM : entity work.BUFG_DCM_80
    port map (
      CLK_IN => clk_frombuf,
      RST    => iResetDCM,
      CLK1X  => clk,
      CLK2X  => clk80,
      LOCK   => dcm_locked);

  oDCMLocked <= dcm_locked;
  oClkNet <= clk;
  oClk80  <= clk80;
  -- no external reset that goes to GSR in ROP chip
  startup_CLK: STARTUP_VIRTEX2_CLK
    port map ( CLK => clk);

  startup_GTS: STARTUP_VIRTEX2_GTS
    port map ( GTS => iTristateToGTS);


-- Xilinx recommends not to use the GSR netwok but the normal routing
-- resources, instead. [Syntehsis and Verification design guide]. They
-- are faster and can be analyzed by the trce tool.
  
--   startup_GSR: STARTUP_VIRTEX2_GSR
--     port map ( GSR => iResetToGSR);

  -- reset on configuration 
  -- ROC is for simulation only, in the implementation, GSR will be used   
--   reset_on_config : ROC
--     port map ( O => roc_reset);

  -- new solution: use general routing resources
  -- this is also fine for synthesis.
  oResetNet <= iResetToGSR or (not dcm_locked);
  
end architecture behavioral;