--******************************************************************************
--* @short    Decoder for the TCS Commands
--*
--*           Register the three TCS commands L1reset, BCReset, L1A
--*           Decode the commands
--*           Generate internal L1A, L1reset, BCReset, ECReset 
--******************************************************************************
--* @author  SAKULIN Hannes  <hsakulin@dsy-srv5.cern.ch>
--* @date    $Date: 2004/12/17 09:30:38 $
--* @version $Revision: 1.2 $
--******************************************************************************
--/
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_std.all;
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.all;
-- pragma translate_on


entity TCSCommandDecoder is
  port (
    iL1A        : in std_logic;          -- Level-1 accept
    iBCReset    : in std_logic;          -- Bunch Counter reset
    iL1Reset    : in std_logic;          -- Level-1 reset

    oL1A       : out std_logic;
    oBCReset   : out std_logic;
    oL1Reset   : out std_logic;
    oECReset   : out std_logic;

    clk        : in std_logic;
    reset      : in std_logic);  

end entity TCSCommandDecoder;


architecture behavioral of TCSCommandDecoder is

  signal l1a_reg     : std_logic;
  signal bcreset_reg : std_logic;
  signal l1reset_reg : std_logic;

  signal sL1Reset    : std_logic;

begin  -- architecture behavioral

  register_tcs: process (clk) is
  begin  -- process register_tcs
    if clk'event and clk = '1' then  -- rising clock edge
      l1a_reg     <= iL1A;
      bcreset_reg <= iBCReset;
      l1reset_reg <= iL1Reset;
    end if;
  end process register_tcs;

  -- Decoding of TCS commands. As dicussed with A. Taurok on 21 July 2004
  --
  -- L1A BCRES L1RES  Command
  -- 0   0     1      L1RES /RESET/RESYNC   reset everything (fifo contents)
  -- 0   1     0      BCRES                 reset only bunch counter
  -- 0   1     1      EVENT CNTR RESET      reset only event counter
  -- 1   0     0      L1A                   L1 accept
  -- 1   0     1      START/STOP RUN*       ignore in GMT
  -- 1   1     0      Concurrent L1A , BCR  L1 accept and BC reset at same time
  -- 1   1     1      ORBIT CNTR RESET      ignore in GMT

    -- decode

  oL1A <= '1' when (l1a_reg = '1' and l1reset_reg = '0') else '0';
  
  sL1Reset <= '1' when (l1a_reg = '0' and bcreset_reg = '0' and l1reset_reg = '1') else '0';

  oL1Reset <= sL1Reset;

  -- do not send a BCreset upon L1reset
  oBCReset <= '1' when (bcreset_reg = '1' and l1reset_reg = '0') else '0';

  -- send an event counter reset also if there is a decoded l1 reset
  oECReset <= '1' when (l1a_reg = '0' and bcreset_reg = '1' and l1reset_reg = '1') or
                       sL1Reset = '1' else '0';
  
end architecture behavioral;