--******************************************************************************
--* @short BUFG_DCM_80     VHDL submodule
--*
--*        DCM with CLK0 and CLK2x output and BUFG drivers
--*        Device: Virtex-II Family
--*
--*        copied fromXilinX Virtex2 UG  -- HS
--*        needs 90 us to lock (at 40 MHz -> 4000 clocks)
--*        reset needs to be high for at least 3 cycles after reconfig
--*
--******************************************************************************
--/
library IEEE;
use IEEE.std_logic_1164.all;

-- Internal feedback only; external feedback io not used
--   Q: feedback 

--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.all;
-- pragma translate_on
--
entity BUFG_DCM_80 is
  port (
    CLK_IN                                 : in  std_logic;
    RST                                    : in  std_logic;
    CLK1X                                  : out std_logic;
    CLK2X                                  : out std_logic;
    LOCK                                   : out std_logic
    );
end BUFG_DCM_80;
--
architecture BUFG_DCM_80_arch of BUFG_DCM_80 is

-- Components Declarations:
  component BUFG
    port (
      I                                    : in  std_logic;
      O                                    : out std_logic
      );
  end component;

  component DCM
-- pragma translate_off
    generic (
      DLL_FREQUENCY_MODE                   :     string  := "LOW";
      DUTY_CYCLE_CORRECTION                :     boolean := true;
      STARTUP_WAIT                         :     boolean := false
      );
-- pragma translate_on
    port ( CLKIN                           : in  std_logic;
           CLKFB                           : in  std_logic;
           DSSEN                           : in  std_logic;
           PSINCDEC                        : in  std_logic;
           PSEN                            : in  std_logic;
           PSCLK                           : in  std_logic;
           RST                             : in  std_logic;
           CLK0                            : out std_logic;
           CLK90                           : out std_logic;
           CLK180                          : out std_logic;
           CLK270                          : out std_logic;
           CLK2X                           : out std_logic;
           CLK2X180                        : out std_logic;
           CLKDV                           : out std_logic;
           CLKFX                           : out std_logic;
           CLKFX180                        : out std_logic;
           LOCKED                          : out std_logic;
           PSDONE                          : out std_logic;
           STATUS                          : out std_logic_vector(7 downto 0)
           );
  end component;
-- Attributes
  attribute DLL_FREQUENCY_MODE             :     string;
  attribute DUTY_CYCLE_CORRECTION          :     string;
  attribute STARTUP_WAIT                   :     string;
  attribute DLL_FREQUENCY_MODE of U_DCM    :     label is "LOW";
  attribute DUTY_CYCLE_CORRECTION of U_DCM :     label is "TRUE";
  attribute STARTUP_WAIT of U_DCM          :     label is "TRUE";
-- Signal Declarations:
  signal GND                               :     std_logic;
  signal CLK0_W, CLK2_W                    :     std_logic;
  signal CLK1X_INT                         :     std_logic;
begin
  GND <= '0';
  
-- DCM Instantiation
  U_DCM: DCM
    port map (
      CLKIN => CLK_IN,
      CLKFB => CLK1X_INT,
      DSSEN => GND,
      PSINCDEC => GND,
      PSEN => GND,
      PSCLK => GND,
      RST => RST,
      CLK0 =>  CLK0_W,
      CLK2X => CLK2_W,
      LOCKED => LOCK
      );
      
-- BUFG Instantiation
  U_BUFG40: BUFG
    port map (
      I => CLK0_W,
      O => CLK1X_INT
      );
 -- CLK1X_INT ...used for internal feedback to DCM
 
  CLK1X <= CLK1X_INT;     -- assign 40 MHz clock to output

-- BUFG Instantiation
  U_BUFG80: BUFG
    port map (
      I => CLK2_W,
      O => CLK2X	-- assign 80 MHz clock to output
      );

end BUFG_DCM_80_arch;