--******************************************************************************
--* @short   Input FPGA (DT version)
--******************************************************************************
--* @author  SAKULIN Hannes  <hsakulin@dsy-srv3.cern.ch>
--* @date    $Date: 2004/12/17 11:24:27 $
--* @version $Revision: 1.10 $
--******************************************************************************
--/
library IEEE;
use IEEE.Std_logic_1164.all;
use WORK.GMTTypes.all;
use WORK.ReadOutBufTypes.all;
use WORK.VMEMux.all;
use WORK.IFVMEAddrMap.all;

-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.all;
-- pragma translate_on
use IEEE.NUMERIC_STD.all;

entity InputFPGAdt is
  port (
    -- CHIP INPUTS    
    DTMu : in TFourInMuons_flat;

    -- out to Logic FPGA and to MIPISO AU
    DTMu_LF : out TFourSyncedMu_flat;
    DTMu_AU : out TFourSyncedMu_flat;

    -- forCOU (DT and CSC chip, only)
    DTPhiCOU : out TPhi_vec(0 to 3);
    DTEtaCOU : out TEtaCOU_vec(0 to 3);
    spare_IND_LFF  : out std_logic;

    -- VME port
    vme_addr       : in    std_logic_vector(19 downto 1);
    vme_data       : inout std_logic_vector(15 downto 0);
    vme_en_IND     : in    std_logic;
    vme_wr_IND     : in    std_logic;
    vme_ndtack_IND : out   std_logic;   -- low active 
    vme_nirq_IND   : out   std_logic;   -- low active 

    -- Readout Data Port
    ro_data_IND    : out std_logic_vector(23 downto 0);
    ro_rdfifo_IND  : in std_logic;
    ro_fetch_IND   : in std_logic;
    l1a_IND        : in std_logic;          -- Level-1 accept
    bcreset_IND    : in std_logic;          -- Bunch Counter reset
    l1reset_IND    : in std_logic;          -- Level-1 reset

    -- Clock and control
    clk_IND        : in  std_logic;
    clk_test_IND   : out std_logic;     -- clock1x from DCM
    clk_out_IND    : out std_logic;     -- clock output for feedback (use optional)
                                        -- same as clk_test
    clk_fb_IND     : in  std_logic;     -- clock feedback input (use optional)
    dcm_locked_IND : out std_logic;     -- DCM is locked => goes to VME chip
    reset_dcm      : in  std_logic;     -- resets DCM
    inactive       : in  std_logic;     -- from front panel button (to GTS)

    status_IND     : out std_logic_vector(1 downto 0);
    test_lemo_IND  : out std_logic;
    test_IND       : out std_logic_vector(3 downto 0);
    reset_IND      : in  std_logic;     -- hard reset from trigger control
                                        --
                                        -- register input
                                        -- same function as level-1 reset
                                        -- or hard reset from trigger control
                                        --
                                        -- generated by VME chip
                                        -- resets only state machines, FFs,
                                        -- counters, error flags
                                        -- but not memories and registers

    dummyb_IND : in std_logic);
end;


architecture behavioral of InputFPGAdt is
  attribute syn_useioff               : boolean;
  attribute syn_useioff of behavioral : architecture is true;
begin
  theChip: entity work.InputFPGA
    generic map (
      input_fpga_idx => 0)                --DT
    port map (
      iMuons     => DTMu,
      oMuonsLF   => DTmu_LF,
      oMuonsAU   => DTmu_AU,
      oPhi       => DTPhiCOU,
      oEta       => DTEtaCOU,
      vme_addr   => vme_addr,
      vme_data   => vme_data,
      vme_en     => vme_en_IND,
      vme_wr     => vme_wr_IND,
      vme_ndtack => vme_ndtack_IND,
      vme_nirq   => vme_nirq_IND,

      ro_data    => ro_data_IND,
      ro_rdfifo  => ro_rdfifo_IND,       
      ro_fetch   => ro_fetch_IND,
      l1a        => l1a_IND,
      bcreset    => bcreset_IND,
      l1reset    => l1reset_IND,   

      clk_input  => clk_IND,
      clk_test   => clk_test_IND,
      clk_out    => clk_out_IND,
      clk_fb     => clk_fb_IND,
      dcm_locked => dcm_locked_IND,
      reset_dcm        => reset_dcm,
      inactive   => inactive,
      status     => status_IND,
      test_lemo  => test_lemo_IND,
      test       => test_IND,
      reset_input=> reset_IND,
      dummyb     => dummyb_IND);
  spare_IND_LFF <= '0';
end architecture behavioral;