--******************************************************************************
--* @short      Input FPGA (FRPC version)
--******************************************************************************
--* @author  SAKULIN Hannes  <hsakulin@dsy-srv3.cern.ch>
--* @date    $Date: 2004/12/17 11:24:27 $
--* @version $Revision: 1.10 $
--******************************************************************************
--/
library IEEE;
use IEEE.Std_logic_1164.all;
use WORK.GMTTypes.all;
use WORK.ReadOutBufTypes.all;
use WORK.VMEMux.all;
use WORK.IFVMEAddrMap.all;

-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.all;
-- pragma translate_on
use IEEE.NUMERIC_STD.all;

entity InputFPGAfrpc is
  port (
    -- CHIP INPUTS    
    fRPCMu : in TFourInMuons_flat;

    -- out to Logic FPGA and to MIPISO AU
    fRPCMu_LF : out TFourSyncedMu_flat;
    fRPCMu_AU : out TFourSyncedMu_flat;

    -- VME port
    vme_addr       : in    std_logic_vector(19 downto 1);
    vme_data       : inout std_logic_vector(15 downto 0);
    vme_en_INF     : in    std_logic;
    vme_wr_INF     : in    std_logic;
    vme_ndtack_INF : out   std_logic;   -- low active 
    vme_nirq_INF   : out   std_logic;   -- low active 

    -- Readout Data Port
    ro_data_INF    : out std_logic_vector(23 downto 0);
    ro_rdfifo_INF  : in std_logic;
    ro_fetch_INF   : in std_logic;
    l1a_INF        : in std_logic;          -- Level-1 accept
    bcreset_INF    : in std_logic;          -- Bunch Counter reset
    l1reset_INF    : in std_logic;          -- Level-1 reset

    -- Clock and control
    clk_INF        : in  std_logic;
    clk_test_INF   : out std_logic;     -- clock1x from DCM
    clk_out_INF    : out std_logic;     -- clock output for feedback (use optional)
                                        -- same as clk_test
    clk_fb_INF     : in  std_logic;     -- clock feedback input (use optional)
    dcm_locked_INF : out std_logic;     -- DCM is locked => goes to VME chip
    reset_dcm      : in  std_logic;     -- resets DCM
    inactive       : in  std_logic;     -- from front panel button (to GTS)

    status_INF     : out std_logic_vector(1 downto 0);
    test_lemo_INF  : out std_logic;
    test_INF       : out std_logic_vector(3 downto 0);
    reset_INF      : in  std_logic;     -- hard reset from trigger control
                                        --
                                        -- register input
                                        -- same function as level-1 reset
                                        -- or hard reset from trigger control
                                        --
                                        -- generated by VME chip
                                        -- resets only state machines, FFs,
                                        -- counters, error flags
                                        -- but not memories and registers

    dummyb_INF : in std_logic);
end;


architecture behavioral of InputFPGAfrpc is

  attribute syn_useioff               : boolean;
  attribute syn_useioff of behavioral : architecture is true;
  signal fRPCPhiCOU_dummy : TPhi_vec(0 to 3);
  signal fRPCEtaCOU_dummy : TEtaCOU_vec(0 to 3);

begin
  theChip: entity work.InputFPGA
    generic map (
      input_fpga_idx => 3)                --FRPC
    port map (
      iMuons     => fRPCMu,
      oMuonsLF   => fRPCmu_LF,
      oMuonsAU   => fRPCmu_AU,
      
      oPhi       => fRPCPhiCOU_dummy,
      oEta       => fRPCEtaCOU_dummy,
      
      vme_addr   => vme_addr,
      vme_data   => vme_data,
      vme_en     => vme_en_INF,
      vme_wr     => vme_wr_INF,
      vme_ndtack => vme_ndtack_INF,
      vme_nirq   => vme_nirq_INF,

      ro_data    => ro_data_INF,
      ro_rdfifo  => ro_rdfifo_INF,       
      ro_fetch   => ro_fetch_INF,
      l1a        => l1a_INF,
      bcreset    => bcreset_INF,
      l1reset    => l1reset_INF,   

      clk_input  => clk_INF,
      clk_test   => clk_test_INF,
      clk_out    => clk_out_INF,
      clk_fb     => clk_fb_INF,
      dcm_locked => dcm_locked_INF,
      reset_dcm        => reset_dcm,
      inactive   => inactive,
      status     => status_INF,
      test_lemo  => test_lemo_INF,
      test       => test_INF,
      
      reset_input=> reset_INF,
      dummyb     => dummyb_INF);
end architecture behavioral;