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--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
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-- You must compile the wrapper file comp6.vhd when simulating
-- the core, comp6. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY comp6 IS
	port (
	A: IN std_logic_VECTOR(5 downto 0);
	B: IN std_logic_VECTOR(5 downto 0);
	A_GE_B: OUT std_logic);
END comp6;

ARCHITECTURE comp6_a OF comp6 IS

component wrapped_comp6
	port (
	A: IN std_logic_VECTOR(5 downto 0);
	B: IN std_logic_VECTOR(5 downto 0);
	A_GE_B: OUT std_logic);
end component;

-- Configuration specification 
	for all : wrapped_comp6 use entity XilinxCoreLib.C_COMPARE_V6_0(behavioral)
		generic map(
			c_has_qa_ge_b => 0,
			c_has_aset => 0,
			c_has_qa_ne_b => 0,
			c_has_qa_lt_b => 0,
			c_has_a_gt_b => 0,
			c_has_a_eq_b => 0,
			c_data_type => 1,
			c_sync_priority => 1,
			c_has_sclr => 0,
			c_has_qa_gt_b => 0,
			c_width => 6,
			c_has_qa_eq_b => 0,
			c_enable_rlocs => 1,
			c_ainit_val => "0",
			c_has_a_le_b => 0,
			c_has_ce => 0,
			c_pipe_stages => 0,
			c_has_aclr => 0,
			c_sync_enable => 0,
			c_has_sset => 0,
			c_has_qa_le_b => 0,
			c_b_constant => 0,
			c_has_a_ge_b => 1,
			c_has_a_ne_b => 0,
			c_has_a_lt_b => 0,
			c_b_value => "0");
BEGIN

U0 : wrapped_comp6
		port map (
			A => A,
			B => B,
			A_GE_B => A_GE_B);
END comp6_a;

-- synopsys translate_on