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-- You must compile the wrapper file lfmatchqual_cscbrpc.vhd when simulating
-- the core, lfmatchqual_cscbrpc. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY lfmatchqual_cscbrpc IS
	port (
	A: IN std_logic_VECTOR(6 downto 0);
	CLK: IN std_logic;
	D: IN std_logic_VECTOR(5 downto 0);
	WE: IN std_logic;
	I_CE: IN std_logic;
	DPRA: IN std_logic_VECTOR(6 downto 0);
	DPO: OUT std_logic_VECTOR(5 downto 0);
	SPO: OUT std_logic_VECTOR(5 downto 0));
END lfmatchqual_cscbrpc;

ARCHITECTURE lfmatchqual_cscbrpc_a OF lfmatchqual_cscbrpc IS

component wrapped_lfmatchqual_cscbrpc
	port (
	A: IN std_logic_VECTOR(6 downto 0);
	CLK: IN std_logic;
	D: IN std_logic_VECTOR(5 downto 0);
	WE: IN std_logic;
	I_CE: IN std_logic;
	DPRA: IN std_logic_VECTOR(6 downto 0);
	DPO: OUT std_logic_VECTOR(5 downto 0);
	SPO: OUT std_logic_VECTOR(5 downto 0));
end component;

-- Configuration specification 
	for all : wrapped_lfmatchqual_cscbrpc use entity XilinxCoreLib.C_DIST_MEM_V6_0(behavioral)
		generic map(
			c_qualify_we => 1,
			c_mem_type => 2,
			c_has_qdpo_rst => 0,
			c_has_qspo => 0,
			c_has_qspo_rst => 0,
			c_has_dpo => 1,
			c_has_qdpo_clk => 0,
			c_has_d => 1,
			c_qce_joined => 0,
			c_width => 6,
			c_reg_a_d_inputs => 1,
			c_latency => 1,
			c_has_spo => 1,
			c_has_we => 1,
			c_depth => 128,
			c_has_i_ce => 1,
			c_default_data_radix => 1,
			c_default_data => "0",
			c_has_dpra => 1,
			c_has_clk => 1,
			c_enable_rlocs => 1,
			c_generate_mif => 1,
			c_has_qspo_ce => 0,
			c_addr_width => 7,
			c_has_qdpo_srst => 0,
			c_mux_type => 0,
			c_has_spra => 0,
			c_has_qdpo => 0,
			c_mem_init_file => "lfmatchqual_cscbrpc.mif",
			c_reg_dpra_input => 0,
			c_has_qspo_srst => 0,
			c_has_rd_en => 0,
			c_read_mif => 1,
			c_sync_enable => 0,
			c_has_qdpo_ce => 0);
BEGIN

U0 : wrapped_lfmatchqual_cscbrpc
		port map (
			A => A,
			CLK => CLK,
			D => D,
			WE => WE,
			I_CE => I_CE,
			DPRA => DPRA,
			DPO => DPO,
			SPO => SPO);
END lfmatchqual_cscbrpc_a;

-- synopsys translate_on