--******************************************************************************
--* @short      Calculate disable hot bits from phi and eta of the DT/CSC muons
--*             from the other chip/chain.
--*
--*             This LUT has to match the disabled regions in
--*             the SortRankEtaPhiLUT in the other Logic FPGA.
--*
--*             Additionally, this unit converts eta from 6 to 4 bits
--******************************************************************************
--* @author  SAKULIN Hannes  <hsakulin@dsy-srv3.cern.ch>
--* @date    $Date: 2005/01/31 15:17:29 $
--* @version $Revision: 1.3 $
--******************************************************************************
--/
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
use WORK.GMTTypes.all;
use WORK.LFTypes.all;
use work.LFVMEAddrMap.all;
use work.LFTiming.all;
use work.VMEMux.all;

entity LFOvlDisableHotUnit is
  
  generic (
    logic_fpga_idx : integer := 0);   -- 0: brl, 1:fwd

  port (
    -- INPUTS
    iPhi : in TPhi_vec(0 to 3);
    iEta : in TEtaCOU_vec(0 to 3);

    -- OUTPUTS
    oDisableHot : out std_logic_vector(0 to 3);

    oEta4_nr    : out TEta4_vec(0 to 3);       -- not registered
    
    -- VME port
    vme_addr       : in    std_logic_vector;
    vme_data       : in    std_logic_vector;
    vme_en         : in    std_logic;
    vme_wr         : in    std_logic;

    vme_data_out   : out   std_logic_vector(15 downto 0);
    vme_en_out     : out   std_logic;
        
    -- Clock and control
    clk            : in    std_logic;
    sinit          : in    std_logic
  );  
  
end entity LFOvlDisableHotUnit;

architecture behavioral of LFOvlDisableHotUnit is

  signal vme_data_out_i   : TVMEData_vec (0 to 7);
  signal vme_en_out_i     : TVMEEnable_vec (0 to 7);

  type TDisHot_vec is array (0 to 3) of std_logic_vector(0 downto 0);
  signal sDisableHot : TDisHot_vec;

begin  -- architecture behavioral

  -----------------------------------------------------------------------------
  -- instantiate Disable Hot LUTs
  -----------------------------------------------------------------------------
  
  mu: for i in 0 to 3 generate
  begin  -- generate sort_rank_DTCSC
    disable_lut: entity work.lfdisablehotlut
      generic map (
        instance_idx        => 1-logic_fpga_idx,
        my_vme_base_address => LF_DisableHotLUT_base(0) + i * LF_DisableHotLUT_size,
        edge                => calc_lf_edge(LF_RLAT_DISHOT))
      port map (
        eta          => iEta(i),
        phi          => iPhi(i),
        disable_hot  => sDisableHot(i),
        
        clk          => clk,
        sinit        => sinit,
        vme_addr     => vme_addr,
        vme_data     => vme_data,
        vme_en       => vme_en,
        vme_wr       => vme_wr,
        vme_data_out => vme_data_out_i(i),
        vme_en_out   => vme_en_out_i(i),
        vme_clk      => clk);
    oDisableHot(i) <= sDisableHot(i)(0);


    -- Convert other DTCSC eta from 6 to 4 bits
    eta_conv: entity work.lfovletaconvlut
      generic map (
        instance_idx        => 4+logic_fpga_idx,  -- attn: here actually
                                                  -- instances 0 and 1 are used
                                                  -- a second time (but in the
                                                  -- other chip)
        my_vme_base_address => LF_OvlEtaConvLUT_base( (4+logic_fpga_idx) / 2 ) + i * LF_OvlEtaConvLUT_size)
      port map (
        eta6         => iEta(i),
        eta_ovl      => oEta4_nr(i),
        
        vme_addr     => vme_addr,
        vme_data     => vme_data,
        vme_en       => vme_en,
        vme_wr       => vme_wr,
        vme_data_out => vme_data_out_i(4+i),
        vme_en_out   => vme_en_out_i(4+i),
        vme_clk      => clk);
  end generate mu;
  
  -- multiplex vme_data_output
  mux_vme(vme_data_out_i, vme_en_out_i, vme_data_out, vme_en_out);
  
end architecture behavioral;