--******************************************************************************
--* @short VME Address Map of Logic FPGA
--*
--* contains both the map for the barrel and the forward logic FPGA
--******************************************************************************
--* @author SAKULIN Hannes <hsakulin@dsy-srv3.cern.ch>
--* @date $Date: 2005/01/31 15:17:30 $
--* @version $Revision: 1.11 $
--******************************************************************************
--/
-- All addresses are in bytes (not words)!
-- TBD: calculate total Address Space!! ( 128k is needed -> 17 Address bits ??)
-- TBD: add number of data bits for each LUT for information
package LFVMEAddrMap is
type LFAddrArr is array (0 to 1) of integer;
type TBaseArray is array (integer range<>) of integer;
-------------------------------------------------------------------------------
-- Registers
-------------------------------------------------------------------------------
constant LF_chip_id0_raddr : integer := 16#00#; -- CHIP ID 0 r
constant LF_chip_id1_raddr : integer := 16#02#; -- CHIP ID 1 r
constant LF_chip_rev0_raddr : integer := 16#04#; -- CHIP rev 0 r
constant LF_chip_rev1_raddr : integer := 16#06#; -- CHIP rev 1 r
constant LF_CDLConfig_addr : TBaseArray (0 to 1) := (
16#20#, -- DT/CSC COU Config (brl chip) CSC/DT COU Config (fwd chip)
16#22# -- bRPC/CSC COU Config (brl chip) fRPC/DT COU Config (fwd chip)
);
constant LF_SortRankOffset_addr : integer := 16#24#;
-- Merge Method Configuration
constant LF_MMConfig_SRK_addr : integer := 16#26#;
constant LF_MMConfig_Phi_addr : integer := 16#28#;
constant LF_MMConfig_Eta_addr : integer := 16#2A#;
constant LF_MMConfig_Pt_addr : integer := 16#2C#;
constant LF_MMConfig_Charge_addr : integer := 16#2E#;
constant LF_MMConfig_MIP_addr : integer := 16#30#;
constant LF_MMConfig_ISO_addr : integer := 16#32#;
constant LF_dummy_raddr : integer := 16#34#;
-------------------------------------------------------------------------------
-- Distributed RAM blocks
-------------------------------------------------------------------------------
constant LF_DistrRam_base : integer := 16#00400#; -- start distributed RAM at
-- 1k
-------------------------------------------------------------------------------
constant LF_MatchQualLUT_size : integer := 256; -- 3*16 instances
constant LF_MatchQualLUT_base : TBaseArray(0 to 2) := (
LF_DistrRam_base, -- DT/bRPC (brl chip) CSC/fRPC(fwd chip)
LF_DistrRam_base + LF_MatchQualLUT_size*16, -- DT/CSC (brl chip) DT/CSC (fwd chip)
LF_DistrRam_base + LF_MatchQualLUT_size*32 -- CSC/bRPC (brl chip) DT/fRPC (fwd chip)
);
-------------------------------------------------------------------------------
constant LF_COUDeltaEtaLUT_size : integer := 512; -- 2*16 instances
constant LF_COUDeltaEtaLUT_base : TBaseArray(0 to 1) := (
LF_DistrRam_base + 16#3000#, -- DT/CSC (brl chip)DT/CSC (fwd chip)
LF_DistrRam_base + 16#3000#+LF_COUDeltaEtaLUT_size*16 -- CSC/bRPC (brl chip)DT/fRPC
);
-------------------------------------------------------------------------------
constant LF_OvlEtaConvLUT_size : integer := 128; -- 3*4 instances
constant LF_OvlEtaConvLUT_base : TBaseArray(0 to 2) := (
LF_DistrRam_base + 16#7000#, -- DT (brl chip) CSC (fwd chip)
LF_DistrRam_base + 16#7000#+LF_OvlEtaConvLUT_size*4, -- bRPC(brl chip) fRPC(fwd chip)
LF_DistrRam_base + 16#7000#+LF_OvlEtaConvLUT_size*8 -- CSC (brl chip) DT (fwd chip)
);
-------------------------------------------------------------------------------
constant LF_EtaConvLUT_size : integer := 128;
constant LF_EtaConvLUT_base : TBaseArray(0 to 1) := (
LF_DistrRam_base + 16#7600#, -- DT CSC
LF_DistrRam_base + 16#7600#+LF_EtaConvLUT_size*4 -- bRPC fRPC
);
-------------------------------------------------------------------------------
constant LF_MergeRankPtQLUT_size : integer := 512;
constant LF_MergeRankPtQLUT_base : LFAddrArr := (
LF_DistrRam_base + 16#7A00#, -- DT CSC
LF_DistrRam_base + 16#7A00# + LF_MergeRankPtQLUT_size*4 -- bRPC fRPC
);
-------------------------------------------------------------------------------
constant LF_PhiProEtaConvLUT_size : integer := 128;
constant LF_PhiProEtaConvLUT_base : TBaseArray(0 to 1) := (
LF_DistrRam_base + 16#8A00#, -- DT CSC
LF_DistrRam_base + 16#8A00#+LF_PhiProEtaConvLUT_size*4 -- bRPC fRPC
);
-------------------------------------------------------------------------------
-- Block RAM blocks
-------------------------------------------------------------------------------
-- -- blocks at 1k
constant LF_BlockRam_base : integer := 16#10000#; -- start block RAM blocks
-- -- at 64k
-- Sort Rank
constant LF_SortRankEtaQLUT_size : integer := 256;
constant LF_SortRankEtaQLUT_base : LFAddrArr := (
LF_BlockRam_base, -- DT CSC
LF_BlockRam_base + LF_SortRankEtaQLUT_size*4 -- bRPC fRPC
);
constant LF_SortRankPtQLUT_size : integer := 256;
constant LF_SortRankPtQLUT_base : LFAddrArr := (
LF_BlockRam_base + 16#800#, -- DT CSC
LF_BlockRam_base + 16#800# + LF_SortRankPtQLUT_size*4 -- bRPC fRPC
);
constant LF_SortRankEtaPhiLUT_size : integer := 4096;
constant LF_SortRankEtaPhiLUT_base : LFAddrArr := (
LF_BlockRam_base + 16#1000#, -- DT CSC
LF_BlockRam_base + 16#1000# + LF_SortRankEtaPhiLUT_size*4 -- bRPC fRPC
);
constant LF_SortRankCombineLUT_size : integer := 2048;
constant LF_SortRankCombineLUT_base : LFAddrArr := (
LF_BlockRam_base + 16#9000#, -- DT CSC
LF_BlockRam_base + 16#9000# + LF_SortRankCombineLUT_size*4 -- bRPC fRPC
);
-- Matching Unit 16x
constant LF_DeltaEtaLUT_size : integer :=2048;
constant LF_DeltaEtaLUT_base : TBaseArray(0 to 0) := (
0 => LF_BlockRam_base + 16#D000# -- DT/bRPC (brl chip) CSC/fRPC (fwd chip)
);
-- PtMix LUT 4x
constant LF_PtMixLUT_size : integer := 1024;
constant LF_PtMixLUT_base : TBaseArray(0 to 0) := (
0 => LF_BlockRam_base + 16#15000#
);
-- next free : LF_BlockRam_base + 16#A000#
-- size in VME is different!!
-- Merge Rank
constant LF_MergeRankEtaQLUT_size : integer := 512;
constant LF_MergeRankEtaQLUT_base : LFAddrArr := (
LF_BlockRam_base + 16#16000#, -- DT CSC
LF_BlockRam_base + 16#16000# + LF_MergeRankEtaQLUT_size*4 -- bRPC fRPC
);
constant LF_MergeRankEtaPhiLUT_size : integer := 2048;
constant LF_MergeRankEtaPhiLUT_base : LFAddrArr := (
LF_BlockRam_base + 16#17000#, -- DT CSC
LF_BlockRam_base + 16#17000# + LF_MergeRankEtaPhiLUT_size*4 -- bRPC fRPC
);
constant LF_MergeRankCombineLUT_size : integer := 1024;
constant LF_MergeRankCombineLUT_base : LFAddrArr := (
LF_BlockRam_base + 16#1B000#, -- DT CSC
LF_BlockRam_base + 16#1B000# + LF_MergeRankCombineLUT_size*4 -- bRPC fRPC
);
-- Disable Hot
constant LF_DisableHotLUT_size : integer := 2048;
constant LF_DisableHotLUT_base : TBaseArray(0 to 0) := (
0 => LF_BlockRam_base + 16#1D000# -- DT (in fwd FPGA), CSC (in brl FPGA)
);
-- Phi Projection
constant LF_PhiProLUT_size : integer := 2048;
constant LF_PhiProLUT_base : LFAddrArr := (
LF_BlockRam_base + 16#1F000#, -- DT CSC
LF_BlockRam_base + 16#1F000# + LF_PhiProLUT_size*4 -- bRPC fRPC
);
end package LFVMEAddrMap;
package body LFVMEAddrMap is
end package body LFVMEAddrMap;