--******************************************************************************
--* @short   Logic FPGA (the whole chip) forward version
--******************************************************************************
--* @author  SAKULIN Hannes  <hsakulin@dsy-srv3.cern.ch>
--* @version $Revision: 1.11 $
--* @date    $Date: 2004/12/16 18:45:45 $
--******************************************************************************
--/
library IEEE;
use IEEE.Std_logic_1164.all;
use WORK.LFTypes.all;
use WORK.GMTTypes.all;
use WORK.LFTiming.all;
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.all;
-- pragma translate_on

entity LogicFPGAfwdchip is
  port (-- CHIP INPUTS
        fRPCmu_LF   : in  TFourSyncedMu_flat;
        CSCmu_LF    : in  TFourSyncedMu_flat;

        -- eta and phi of DT/CSC from other stream for cancel-out
        DTPhiCOU     : in TPhi_vec(0 to 3);
        DTEtaCOU     : in TEtaCOU_vec(0 to 3);
        spare_IND_LFF : in std_logic;

        -- MIP & ISO bits 
        fRPCisMIP,
        CSCisMIP,
        fRPCisISO,
        CSCisISO       : in std_logic_vector (0 to 3);
        spare_AUF_LFF  : in std_logic;
        
        -- cancel-out links
        DTisMatched : in std_logic_vector (0 to 3);
        CancelCSC   : in std_logic_vector (0 to 3);
        spare_LFF_LFB : out std_logic;
        
        -- CHIP OUTPUTS
        OutMuons_fwd   : out TFourGMTMu_flat;
        SortRanks_fwd  : out TSortRank_vector(0 to 3);
        IdxBits_fwd    : out TIndexBits_vector(0 to 3);
        IsRPCMu_fwd    : out std_logic_vector (0 to 3);
        
        CSCisMatched   : out std_logic_vector (0 to 3);
        CancelDT       : out std_logic_vector (0 to 3);
        
        -- TBD: add extra quality bits with muon indices, later 

        
        -- test outputs - for behavioral simu only
-- synthesis translate_off
        oPairMatrix      : out TPairMatrix;
        oPairMatrix1     : out TPairMatrix;
        oPairMatrix2     : out TPairMatrix;
        oMQMatrix        : out   TMQMatrix;
        oCancelBits1   : out std_logic_vector(0 to 7);
        oCancelBits2   : out std_logic_vector(0 to 7);
-- synthesis translate_on
       
        Dummy_LFF : in std_logic;       -- changed to input
        -- VME port
        vme_addr       : in    std_logic_vector(19 downto 1);
        vme_data       : inout std_logic_vector(15 downto 0);
        vme_en_LFF     : in    std_logic;
        vme_wr_LFF     : in    std_logic;
        vme_ndtack_LFF : out   std_logic;  -- low active 
        vme_nirq_LFF   : out   std_logic;  -- low active 

        -- Clock and control
        clk_LFF        : in    std_logic;
        clk_test_LFF   : out   std_logic;   -- clock1x from DCM
        clk_out_LFF    : out   std_logic;   -- clock output for feedback (use optional)
                                            -- same as clk_test
        clk_fb_LFF     : in    std_logic;   -- clock feedback input (use optional)
        
        dcm_locked_LFF : out   std_logic;   -- DCM is locked => goes to VME chip

        reset_dcm            : in    std_logic;   -- crate reset (crate reset button and after
                                            -- power-up)  => resets DCM
        inactive       : in    std_logic;   -- from front panel button (to GTS)
    
        
        status_LFF     : out   std_logic_vector(1 downto 0);
        test_LFF       : out   std_logic_vector(3 downto 0);
        reset_LFF      : in    std_logic);  -- hard reset from trigger control
                                            --
                                            -- register input
                                            -- same function as level-1 reset
                                            -- or hard reset from trigger control
                                            --
                                            -- generated by VME chip
                                            -- resets only state machines, FFs,
                                            -- counters, error flags
                                            -- but not memories and registers
end;


architecture behavioral of LogicFPGAfwdchip is
  attribute syn_useioff               : boolean;
  attribute syn_useioff of behavioral : architecture is true;
  signal spare_or : std_logic;
  begin

    spare_or <= spare_AUF_LFF or spare_IND_LFF;
    
  theChip: entity work.LogicFPGA
    generic map (
      logic_fpga_idx  => 1) -- forward: 1
    port map (
      iRPCmuons            => fRPCmu_LF,
      iDTCSCmuons          => CSCmu_LF,
      
      iPhiCOU              => DTPhiCOU,
      iEtaCOU              => DTEtaCOU,
      
      
      iRPCisMIP            => fRPCisMIP,
      iDTCSCisMIP          => CSCisMIP,
      iRPCisISO            => fRPCisISO,
      iDTCSCisISO          => CSCisISO,
      
      iOtherDTCSCisMatched => DTisMatched,
      iCancelDTCSC         => CancelCSC,

      oOutMuons            => OutMuons_fwd,
      oSortRanks           => SortRanks_fwd,
      oIdxBits             => IdxBits_fwd,
      oIsRPCMu             => IsRPCMu_fwd,

      oDTCSCisMatched      => CSCisMatched,
      oCancelOtherDTCSC    => CancelDT,
      
-- synthesis translate_off
      oPairMatrix          => oPairMatrix,
      oPairMatrix1         => oPairMatrix1,
      oPairMatrix2         => oPairMatrix2,
      oMQMatrix            => oMQMatrix,
	oCancelBits1   => oCancelBits1,
	oCancelBits2   => oCancelBits2,

-- synthesis translate_on
      oDummy               => Dummy_LFF,
      vme_addr             => vme_addr,
      vme_data             => vme_data,
      vme_en               => vme_en_LFF,
      vme_wr               => vme_wr_LFF,
      vme_ndtack           => vme_ndtack_LFF,
      vme_nirq             => vme_nirq_LFF,
      
      clk_input            => clk_LFF,
      clk_test             => clk_test_LFF,
      clk_out              => clk_out_LFF,
      clk_fb               => clk_fb_LFF,
      dcm_locked           => dcm_locked_LFF,
      reset_dcm                  => reset_dcm,
      inactive             => inactive,
      status               => status_LFF,
      test                 => test_LFF,
      spare                => spare_or,
      reset_input          => reset_LFF);

      spare_LFF_LFB <= '0';

end architecture behavioral;