--******************************************************************************
--* @short   Phi Projection Unit in MIAU Chip (for 1 muon)
--******************************************************************************
--* @author  SAKULIN Hannes  <hsakulin@dsy-srv3.cern.ch>
--* @version $Revision: 1.3 $
--* @date    $Date: 2004/12/16 18:38:54 $
--******************************************************************************
--/
library IEEE;
use IEEE.Std_logic_1164.all;
use WORK.GMTTypes.all;
use work.MIAUVMEAddrMap.all;

entity MIAUPhiProUnit is
  generic (
    instance_idx : integer       := 0;  -- type
    idxmuon      : integer       := 0);      -- number of muon
  port (iCh            : in  std_logic;                      -- charge
        iPt            : in  std_logic_vector (4 downto 0);  -- 5 bit pT
        iEta           : in  std_logic_vector (5 downto 0);  -- 6 bit eta
        iPhi           : in  std_logic_vector (7 downto 0);  -- 6 bit phi
        oPhiSelectBits : out std_logic_vector (17 downto 0);     -- phi select bits

        -- VME port
        vme_addr       : in    std_logic_vector;
        vme_data       : in    std_logic_vector;
        vme_en         : in    std_logic;
        vme_wr         : in    std_logic;

        vme_data_out   : out   vme_dout_vec (0 to 2);
        vme_en_out     : out   vme_enout_vec (0 to 2);

        -- Clock and control
        clk            : in    std_logic;
        sinit          : in    std_logic);
end;
  

architecture behavioral of MIAUPhiProUnit is

  signal charge_i   : std_logic_vector (0 downto 0);   
  signal phi_fine_i : std_logic_vector (2 downto 0);   -- lower 3 bits of input phi
  signal phi_coarse_i : std_logic_vector (4 downto 0); -- upper 5 bits of input phi
  signal eta4_i : std_logic_vector (3 downto 0);       -- 4-bit eta
  
  signal cphi_fine_i : std_logic_vector(0 downto 0);
  signal cphi_ofs_i  : std_logic_vector(2 downto 0);

  signal nclk : std_logic;
begin
--  the_EtaConvLUT: work.

  theEtaConvLUT: entity work.miauetaconvlut
    generic map (
      instance_idx        => instance_idx,
      my_vme_base_address => MIAU_EtaConvLUT_base(instance_idx mod 4) + idxmuon * MIAU_EtaConvLUT_size)
    port map (
      eta_in   => iEta,
      eta_out  => eta4_i,
      
      vme_addr => vme_addr,
      vme_data => vme_data,
      vme_en   => vme_en,
      vme_wr   => vme_wr,
      vme_data_out => vme_data_out(0),
      vme_en_out => vme_en_out(0),
      vme_clk => clk);

  charge_i(0) <= iCh;

  -- split input phi
  phi_fine_i <= iPhi (2 downto 0);
  -- tag empty muons with phi_coarse = 11111
  phi_coarse_i <= iPhi (7 downto 3) when iPt /= "00000" else "11111";
  
  nclk <= not clk;

  thePhiPro1LUT: entity work.miauphipro1lut
    generic map (
      instance_idx        => instance_idx,
      my_vme_base_address => MIAU_PhiPro1LUT_base(instance_idx mod 4) + idxmuon * MIAU_PhiPro1LUT_size )
    port map (
      phi_fine  => phi_fine_i,
      eta       => eta4_i,
      pt        => iPt,
      charge    => charge_i,
      cphi_fine => cphi_fine_i,
      cphi_ofs  => cphi_ofs_i,
      
      clk       => nclk,
      sinit     => sinit,

      vme_addr  => vme_addr,
      vme_data  => vme_data,
      vme_en    => vme_en,
      vme_wr    => vme_wr,
      vme_data_out => vme_data_out(1),
      vme_en_out => vme_en_out(1),
      vme_clk   => clk);


  thePhiPro2LUT: entity work.miauphipro2lut
    generic map (
      instance_idx        => instance_idx,
      my_vme_base_address => MIAU_PhiPro2LUT_base(instance_idx mod 4) + idxmuon * MIAU_PhiPro2LUT_size)
    port map (
      cphi_start => phi_coarse_i,
      cphi_fine  => cphi_fine_i,
      cphi_ofs   => cphi_ofs_i,
      charge     => charge_i,
      phi_sel    => oPhiSelectBits,
      
      clk        => clk,
      sinit      => sinit,

      vme_addr   => vme_addr,
      vme_data   => vme_data,
      vme_en     => vme_en,
      vme_wr     => vme_wr,
      vme_data_out => vme_data_out(2),
      vme_en_out => vme_en_out(2),
      vme_clk   => clk);
  
end architecture behavioral;