--******************************************************************************
--* @short   Timing of MIAU chip
--******************************************************************************
--* @author  SAKULIN Hannes  <hsakulin@dsy-srv3.cern.ch>
--* @version $Revision: 1.3 $
--* @date    $Date: 2004/12/16 18:34:33 $
--******************************************************************************
--/
library ieee;
use ieee.std_logic_1164.all;

package MIAUTiming is

-- define constants for all the clock edges, here
  
constant MIAU_EDGE_INPUT : std_logic := '1'; -- clk edge for muon data input (1 = rising)

constant MIAU_EDGE_MIP_INPUT : std_logic := '1';    -- rising edge for MIP bits input
constant MIAU_EDGE_QUIET_INPUT : std_logic := '0';  -- falling edge for Quiet bits input

constant MIAU_EDGE_OUTPUT : std_logic := '1';

constant MIAU_EDGE_VME : std_logic := '1'; -- clk edge for VME  data I/O (1 = rising)

end package MIAUTiming;


package body MIAUTiming is

end package body MIAUTiming;