--******************************************************************************
--* @short      Mip And Iso Assignment Unit (Barrel version)
--******************************************************************************
--* @author  SAKULIN Hannes  <hsakulin@dsy-srv3.cern.ch>
--* @version $Revision: 1.6 $
--* @date    $Date: 2004/12/16 18:33:55 $
--******************************************************************************
--/
library IEEE;
use IEEE.Std_logic_1164.all;
use WORK.GMTTypes.all;

entity MipIsoAUbrl is
  port (bRPCmu_AU   : in TFourSyncedMu_flat;
        DTmu_AU     : in TFourSyncedMu_flat;
        bMQbits     : in    std_logic_vector(0 to 10*18-1); -- 7 for barrel
        bRPCisMIP,
        DTisMIP,
        bRPCisISO,
        DTisISO    : out std_logic_vector (0 to 3);
        spare_AUB_LFB : out std_logic;

        -- test outputs - for behavioral simu only
-- synthesis translate_off
        oPhiSelBits : out TPhiSelBits_vec (0 to 15);
        oEtaSelBits : out TEtaSelBits_vec (0 to 15);
-- synthesis translate_on
        Dummy_AUB  : in std_logic;

        -- VME port
        vme_addr       : in    std_logic_vector (19 downto 1);
        vme_data       : inout std_logic_vector (15 downto 0);
        vme_en_AUB     : in    std_logic;
        vme_wr_AUB     : in    std_logic;
        vme_ndtack_AUB : out   std_logic;  -- low active 
        vme_nirq_AUB   : out   std_logic;  -- low active 


        -- Clock and control
        clk_AUB        : in    std_logic;
        clk_test_AUB   : out   std_logic;   -- clock1x from DCM
        clk_out_AUB    : out std_logic;     -- clock output for feedback (use optional)
                                            -- same as clk_test
        clk_fb_AUB     : in std_logic;      -- clock feedback input (use optional)
        
        dcm_locked_AUB : out   std_logic;   -- DCM is locked => goes to VME chip

        reset_dcm            : in    std_logic;   -- crate reset (crate reset button and after
                                            -- power-up)  => resets DCM
        inactive       : in    std_logic;   -- from front panel button (to GTS)
    
        
        status_AUB     : out   std_logic_vector(1 downto 0); 
        test_AUB       : out   std_logic_vector(3 downto 0); 
        reset_AUB      : in    std_logic);  -- hard reset from trigger control
                                            --
                                            -- register input
                                            -- same function as level-1 reset
                                            -- or hard reset from trigger control
                                            --
                                            -- generated by VME chip
                                            -- resets only state machines, FFs,
                                            -- counters, error flags
                                            -- but not memories and registers
end;

architecture behavioral of MipIsoAUbrl is
  attribute syn_useioff               : boolean;
  attribute syn_useioff of behavioral : architecture is true;

begin

  theChip: entity work.MipIsoAU
    generic map (
      Neta            => 10,
      miau_idx        => 0)
    port map (
      iRPCmuons   => bRPCmu_AU,
      iDTCSCmuons => DTmu_AU,
      iMQbits     => bMQbits,
      oRPCisMIP   => bRPCisMIP,
      oDTCSCisMIP => DTisMIP,
      oRPCisISO   => bRPCisISO,
      oDTCSCisISO => DTisISO,
      
-- synthesis translate_off
      oPhiSelBits =>  oPhiSelBits, 
      oEtaSelBits =>  oEtaSelBits, 
-- synthesis translate_on
      oDummy      => Dummy_AUB,
      
      vme_addr    => vme_addr,
      vme_data    => vme_data,
      vme_en      => vme_en_AUB,
      vme_wr      => vme_wr_AUB,
      vme_ndtack  => vme_ndtack_AUB,
      vme_nirq    => vme_nirq_AUB,
      
      clk_input   => clk_AUB,
      clk_test    => clk_test_AUB,
      clk_fb      => clk_fb_AUB,
      clk_out     => clk_out_AUB,
      dcm_locked  => dcm_locked_AUB,
      reset_dcm         => reset_dcm,
      inactive    => inactive,
      status      => status_AUB,
      test        => test_AUB,
      reset_input => reset_AUB);

  spare_AUB_LFB <= '0';

end architecture behavioral;