--******************************************************************************
--* @short Mip And Iso Assignment Unit Forward Chip
--*
--* This wrapper just chnages the names of the MIP/ISO bits
--******************************************************************************
--* @author SAKULIN Hannes <hsakulin@dsy-srv3.cern.ch>
--* @version $Revision: 1.7 $
--* @date $Date: 2004/12/16 18:33:54 $
--******************************************************************************
--/
library IEEE;
use IEEE.Std_logic_1164.all;
use WORK.GMTTypes.all;
entity MipIsoAUfwdchip is
port (fRPCmu_AU : in TFourSyncedMu_flat;
CSCmu_AU : in TFourSyncedMu_flat;
-- MIP/QUIET bits as defined on cables and backplane
-- copied from MIPISObits.xls
MQF3_6_0,
MQF3_6_1,
MQF3_6_8,
MQF3_6_9,
MQF4_6_4,
MQF4_6_5,
MQF7_6_0,
MQF7_6_1,
MQF7_6_8,
MQF7_6_9,
MQF8_6_4,
MQF8_6_5,
MQF11_6_0,
MQF11_6_1,
MQF11_6_8,
MQF11_6_9,
MQF12_6_4,
MQF12_6_5,
MQF3_45_1,
MQF3_45_3,
MQF3_45_9,
MQF3_45_11,
MQF4_45_5,
MQF4_45_7,
MQF7_45_1,
MQF7_45_3,
MQF7_45_9,
MQF7_45_11,
MQF8_45_5,
MQF8_45_7,
MQF11_45_1,
MQF11_45_3,
MQF11_45_9,
MQF11_45_11,
MQF12_45_5,
MQF12_45_7,
MQF3_45_0,
MQF3_45_2,
MQF3_45_8,
MQF3_45_10,
MQF4_45_4,
MQF4_45_6,
MQF7_45_0,
MQF7_45_2,
MQF7_45_8,
MQF7_45_10,
MQF8_45_4,
MQF8_45_6,
MQF11_45_0,
MQF11_45_2,
MQF11_45_8,
MQF11_45_10,
MQF12_45_4,
MQF12_45_6,
MQF1_23_1,
MQF1_23_3,
MQF1_23_9,
MQF1_23_11,
MQF2_23_5,
MQF2_23_7,
MQF5_23_1,
MQF5_23_3,
MQF5_23_9,
MQF5_23_11,
MQF6_23_5,
MQF6_23_7,
MQF9_23_1,
MQF9_23_3,
MQF9_23_9,
MQF9_23_11,
MQF10_23_5,
MQF10_23_7,
MQF1_23_0,
MQF1_23_2,
MQF1_23_8,
MQF1_23_10,
MQF2_23_4,
MQF2_23_6,
MQF5_23_0,
MQF5_23_2,
MQF5_23_8,
MQF5_23_10,
MQF6_23_4,
MQF6_23_6,
MQF9_23_0,
MQF9_23_2,
MQF9_23_8,
MQF9_23_10,
MQF10_23_4,
MQF10_23_6,
MQF1_23_4,
MQF1_23_6,
MQF2_23_0,
MQF2_23_2,
MQF2_23_8,
MQF2_23_10,
MQF5_23_4,
MQF5_23_6,
MQF6_23_0,
MQF6_23_2,
MQF6_23_8,
MQF6_23_10,
MQF9_23_4,
MQF9_23_6,
MQF10_23_0,
MQF10_23_2,
MQF10_23_8,
MQF10_23_10,
MQF1_23_5,
MQF1_23_7,
MQF2_23_1,
MQF2_23_3,
MQF2_23_9,
MQF2_23_11,
MQF5_23_5,
MQF5_23_7,
MQF6_23_1,
MQF6_23_3,
MQF6_23_9,
MQF6_23_11,
MQF9_23_5,
MQF9_23_7,
MQF10_23_1,
MQF10_23_3,
MQF10_23_9,
MQF10_23_11,
MQF3_45_4,
MQF3_45_6,
MQF4_45_0,
MQF4_45_2,
MQF4_45_8,
MQF4_45_10,
MQF7_45_4,
MQF7_45_6,
MQF8_45_0,
MQF8_45_2,
MQF8_45_8,
MQF8_45_10,
MQF11_45_4,
MQF11_45_6,
MQF12_45_0,
MQF12_45_2,
MQF12_45_8,
MQF12_45_10,
MQF3_45_5,
MQF3_45_7,
MQF4_45_1,
MQF4_45_3,
MQF4_45_9,
MQF4_45_11,
MQF7_45_5,
MQF7_45_7,
MQF8_45_1,
MQF8_45_3,
MQF8_45_9,
MQF8_45_11,
MQF11_45_5,
MQF11_45_7,
MQF12_45_1,
MQF12_45_3,
MQF12_45_9,
MQF12_45_11,
MQF3_6_4,
MQF3_6_5,
MQF4_6_0,
MQF4_6_1,
MQF4_6_8,
MQF4_6_9,
MQF7_6_4,
MQF7_6_5,
MQF8_6_0,
MQF8_6_1,
MQF8_6_8,
MQF8_6_9,
MQF11_6_4,
MQF11_6_5,
MQF12_6_0,
MQF12_6_1,
MQF12_6_8,
MQF12_6_9 : in std_logic;
-- fMQbits : in std_logic_vector(0 to 10*18-1);
fRPCisMIP,
CSCisMIP,
fRPCisISO,
CSCisISO : out std_logic_vector (0 to 3);
spare_AUF_LFF : out std_logic;
-- test outputs - for behavioral simu only
-- synthesis translate_off
oPhiSelBits : out TPhiSelBits_vec (0 to 15);
oEtaSelBits : out TEtaSelBits_vec (0 to 15);
-- synthesis translate_on
Dummy_AUF : in std_logic;
-- VME port
vme_addr : in std_logic_vector (19 downto 1);
vme_data : inout std_logic_vector (15 downto 0);
vme_en_AUF : in std_logic;
vme_wr_AUF : in std_logic;
vme_ndtack_AUF : out std_logic; -- low active
vme_nirq_AUF : out std_logic; -- low active
-- Clock and control
clk_AUF : in std_logic;
clk_test_AUF : out std_logic; -- clock1x from DCM
clk_out_AUF : out std_logic; -- clock output for feedback (use optional)
-- same as clk_test
clk_fb_AUF : in std_logic; -- clock feedback input (use optional)
dcm_locked_AUF : out std_logic; -- DCM is locked => goes to VME chip
reset_dcm : in std_logic; -- crate reset (crate reset button and after
-- power-up) => resets DCM
inactive : in std_logic; -- from front panel button (to GTS)
status_AUF : out std_logic_vector(1 downto 0);
test_AUF : out std_logic_vector(3 downto 0);
reset_AUF : in std_logic); -- hard reset from trigger control
--
-- register input
-- same function as level-1 reset
-- or hard reset from trigger control
--
-- generated by VME chip
-- resets only state machines, FFs,
-- counters, error flags
-- but not memories and registers
end;
architecture behavioral of MipIsoAUfwdchip is
attribute syn_useioff : boolean;
attribute syn_useioff of behavioral : architecture is true;
signal MQfwd : std_logic_vector(0 to 10*18-1);
begin
-- mapping of MIP/QUIET bits as defined on cables and backplane
-- copied from MIPISObits.xls
MQfwd(0) <= MQF3_6_0;
MQfwd(1) <= MQF3_6_1;
MQfwd(2) <= MQF3_6_8;
MQfwd(3) <= MQF3_6_9;
MQfwd(4) <= MQF4_6_4;
MQfwd(5) <= MQF4_6_5;
MQfwd(6) <= MQF7_6_0;
MQfwd(7) <= MQF7_6_1;
MQfwd(8) <= MQF7_6_8;
MQfwd(9) <= MQF7_6_9;
MQfwd(10) <= MQF8_6_4;
MQfwd(11) <= MQF8_6_5;
MQfwd(12) <= MQF11_6_0;
MQfwd(13) <= MQF11_6_1;
MQfwd(14) <= MQF11_6_8;
MQfwd(15) <= MQF11_6_9;
MQfwd(16) <= MQF12_6_4;
MQfwd(17) <= MQF12_6_5;
MQfwd(18) <= MQF3_45_1;
MQfwd(19) <= MQF3_45_3;
MQfwd(20) <= MQF3_45_9;
MQfwd(21) <= MQF3_45_11;
MQfwd(22) <= MQF4_45_5;
MQfwd(23) <= MQF4_45_7;
MQfwd(24) <= MQF7_45_1;
MQfwd(25) <= MQF7_45_3;
MQfwd(26) <= MQF7_45_9;
MQfwd(27) <= MQF7_45_11;
MQfwd(28) <= MQF8_45_5;
MQfwd(29) <= MQF8_45_7;
MQfwd(30) <= MQF11_45_1;
MQfwd(31) <= MQF11_45_3;
MQfwd(32) <= MQF11_45_9;
MQfwd(33) <= MQF11_45_11;
MQfwd(34) <= MQF12_45_5;
MQfwd(35) <= MQF12_45_7;
MQfwd(36) <= MQF3_45_0;
MQfwd(37) <= MQF3_45_2;
MQfwd(38) <= MQF3_45_8;
MQfwd(39) <= MQF3_45_10;
MQfwd(40) <= MQF4_45_4;
MQfwd(41) <= MQF4_45_6;
MQfwd(42) <= MQF7_45_0;
MQfwd(43) <= MQF7_45_2;
MQfwd(44) <= MQF7_45_8;
MQfwd(45) <= MQF7_45_10;
MQfwd(46) <= MQF8_45_4;
MQfwd(47) <= MQF8_45_6;
MQfwd(48) <= MQF11_45_0;
MQfwd(49) <= MQF11_45_2;
MQfwd(50) <= MQF11_45_8;
MQfwd(51) <= MQF11_45_10;
MQfwd(52) <= MQF12_45_4;
MQfwd(53) <= MQF12_45_6;
MQfwd(54) <= MQF1_23_1;
MQfwd(55) <= MQF1_23_3;
MQfwd(56) <= MQF1_23_9;
MQfwd(57) <= MQF1_23_11;
MQfwd(58) <= MQF2_23_5;
MQfwd(59) <= MQF2_23_7;
MQfwd(60) <= MQF5_23_1;
MQfwd(61) <= MQF5_23_3;
MQfwd(62) <= MQF5_23_9;
MQfwd(63) <= MQF5_23_11;
MQfwd(64) <= MQF6_23_5;
MQfwd(65) <= MQF6_23_7;
MQfwd(66) <= MQF9_23_1;
MQfwd(67) <= MQF9_23_3;
MQfwd(68) <= MQF9_23_9;
MQfwd(69) <= MQF9_23_11;
MQfwd(70) <= MQF10_23_5;
MQfwd(71) <= MQF10_23_7;
MQfwd(72) <= MQF1_23_0;
MQfwd(73) <= MQF1_23_2;
MQfwd(74) <= MQF1_23_8;
MQfwd(75) <= MQF1_23_10;
MQfwd(76) <= MQF2_23_4;
MQfwd(77) <= MQF2_23_6;
MQfwd(78) <= MQF5_23_0;
MQfwd(79) <= MQF5_23_2;
MQfwd(80) <= MQF5_23_8;
MQfwd(81) <= MQF5_23_10;
MQfwd(82) <= MQF6_23_4;
MQfwd(83) <= MQF6_23_6;
MQfwd(84) <= MQF9_23_0;
MQfwd(85) <= MQF9_23_2;
MQfwd(86) <= MQF9_23_8;
MQfwd(87) <= MQF9_23_10;
MQfwd(88) <= MQF10_23_4;
MQfwd(89) <= MQF10_23_6;
MQfwd(90) <= MQF1_23_4;
MQfwd(91) <= MQF1_23_6;
MQfwd(92) <= MQF2_23_0;
MQfwd(93) <= MQF2_23_2;
MQfwd(94) <= MQF2_23_8;
MQfwd(95) <= MQF2_23_10;
MQfwd(96) <= MQF5_23_4;
MQfwd(97) <= MQF5_23_6;
MQfwd(98) <= MQF6_23_0;
MQfwd(99) <= MQF6_23_2;
MQfwd(100) <= MQF6_23_8;
MQfwd(101) <= MQF6_23_10;
MQfwd(102) <= MQF9_23_4;
MQfwd(103) <= MQF9_23_6;
MQfwd(104) <= MQF10_23_0;
MQfwd(105) <= MQF10_23_2;
MQfwd(106) <= MQF10_23_8;
MQfwd(107) <= MQF10_23_10;
MQfwd(108) <= MQF1_23_5;
MQfwd(109) <= MQF1_23_7;
MQfwd(110) <= MQF2_23_1;
MQfwd(111) <= MQF2_23_3;
MQfwd(112) <= MQF2_23_9;
MQfwd(113) <= MQF2_23_11;
MQfwd(114) <= MQF5_23_5;
MQfwd(115) <= MQF5_23_7;
MQfwd(116) <= MQF6_23_1;
MQfwd(117) <= MQF6_23_3;
MQfwd(118) <= MQF6_23_9;
MQfwd(119) <= MQF6_23_11;
MQfwd(120) <= MQF9_23_5;
MQfwd(121) <= MQF9_23_7;
MQfwd(122) <= MQF10_23_1;
MQfwd(123) <= MQF10_23_3;
MQfwd(124) <= MQF10_23_9;
MQfwd(125) <= MQF10_23_11;
MQfwd(126) <= MQF3_45_4;
MQfwd(127) <= MQF3_45_6;
MQfwd(128) <= MQF4_45_0;
MQfwd(129) <= MQF4_45_2;
MQfwd(130) <= MQF4_45_8;
MQfwd(131) <= MQF4_45_10;
MQfwd(132) <= MQF7_45_4;
MQfwd(133) <= MQF7_45_6;
MQfwd(134) <= MQF8_45_0;
MQfwd(135) <= MQF8_45_2;
MQfwd(136) <= MQF8_45_8;
MQfwd(137) <= MQF8_45_10;
MQfwd(138) <= MQF11_45_4;
MQfwd(139) <= MQF11_45_6;
MQfwd(140) <= MQF12_45_0;
MQfwd(141) <= MQF12_45_2;
MQfwd(142) <= MQF12_45_8;
MQfwd(143) <= MQF12_45_10;
MQfwd(144) <= MQF3_45_5;
MQfwd(145) <= MQF3_45_7;
MQfwd(146) <= MQF4_45_1;
MQfwd(147) <= MQF4_45_3;
MQfwd(148) <= MQF4_45_9;
MQfwd(149) <= MQF4_45_11;
MQfwd(150) <= MQF7_45_5;
MQfwd(151) <= MQF7_45_7;
MQfwd(152) <= MQF8_45_1;
MQfwd(153) <= MQF8_45_3;
MQfwd(154) <= MQF8_45_9;
MQfwd(155) <= MQF8_45_11;
MQfwd(156) <= MQF11_45_5;
MQfwd(157) <= MQF11_45_7;
MQfwd(158) <= MQF12_45_1;
MQfwd(159) <= MQF12_45_3;
MQfwd(160) <= MQF12_45_9;
MQfwd(161) <= MQF12_45_11;
MQfwd(162) <= MQF3_6_4;
MQfwd(163) <= MQF3_6_5;
MQfwd(164) <= MQF4_6_0;
MQfwd(165) <= MQF4_6_1;
MQfwd(166) <= MQF4_6_8;
MQfwd(167) <= MQF4_6_9 ;
MQfwd(168) <= MQF7_6_4 ;
MQfwd(169) <= MQF7_6_5 ;
MQfwd(170) <= MQF8_6_0 ;
MQfwd(171) <= MQF8_6_1 ;
MQfwd(172) <= MQF8_6_8 ;
MQfwd(173) <= MQF8_6_9 ;
MQfwd(174) <= MQF11_6_4 ;
MQfwd(175) <= MQF11_6_5 ;
MQfwd(176) <= MQF12_6_0 ;
MQfwd(177) <= MQF12_6_1 ;
MQfwd(178) <= MQF12_6_8 ;
MQfwd(179) <= MQF12_6_9 ;
theChip: entity work.MipIsoAUfwd
port map (
fRPCmu_AU => fRPCmu_AU,
CSCmu_AU => CSCmu_AU,
fMQbits => MQfwd,
fRPCisMIP => fRPCisMIP,
CSCisMIP => CSCisMIP,
fRPCisISO => fRPCisISO,
CSCisISO => CSCisISO,
spare_AUF_LFF => spare_AUF_LFF,
-- synthesis translate_off
oPhiSelBits => oPhiSelBits,
oEtaSelBits => oEtaSelBits,
-- synthesis translate_on
Dummy_AUF => Dummy_AUF,
vme_addr => vme_addr,
vme_data => vme_data,
vme_en_AUF => vme_en_AUF,
vme_wr_AUF => vme_wr_AUF,
vme_ndtack_AUF => vme_ndtack_AUF,
vme_nirq_AUF => vme_nirq_AUF,
clk_AUF => clk_AUF,
clk_test_AUF => clk_test_AUF,
clk_out_AUF => clk_out_AUF,
clk_fb_AUF => clk_fb_AUF,
dcm_locked_AUF => dcm_locked_AUF,
reset_dcm => reset_dcm,
inactive => inactive,
status_AUF => status_AUF,
test_AUF => test_AUF,
reset_AUF => reset_AUF);
end architecture behavioral;