-------------------------------------------------------------------------------
-- Title      : Top of JTAG Controller for vme-chip of GT-boards
-- Project    : 
-------------------------------------------------------------------------------
-- File       : jtag_ctrl.vhd
-- Author     : H. Bergauer
-- Company    : 
-------------------------------------------------------------------------------
-- Description: top module for VIEWDRAW of JTAG Controller 
-------------------------------------------------------------------------------
-- $Date: 2004/12/09 13:22:49 $
-- $Revision: 1.3 $
-------------------------------------------------------------------------------

library IEEE;
library work;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

LIBRARY altera;
USE altera.maxplus2.ALL;

------------------------------------------------------------------------
-- Entity Declaration
------------------------------------------------------------------------

entity jtag_ctrl is
  port (
    addr       : in    std_logic_vector(3 downto 1);
    data       : inout    std_logic_vector(7 downto 0);
    clk        : in    std_logic;
    en_jtag    : in    std_logic;
--    dssync     : in    std_logic;
    write      : in    std_logic;
    nsysres    : in    std_logic;
    dtack      : out   std_logic;
    tck_0      : out   std_logic;
    tck_1      : out   std_logic;
    tms_0      : out   std_logic;
    tms_1      : out   std_logic;
    tdo_0      : out   std_logic;
    tdo_1      : out   std_logic;
    tdi_0      : in    std_logic;
    tdi_1      : in    std_logic
);
end;

------------------------------------------------------------------------
-- Architecture declaration
------------------------------------------------------------------------

architecture rtl of jtag_ctrl is

--  address parameters for JTAGController
  constant base_address : integer := 0;
  constant address_increment : integer := 2;
  constant addr_high : integer := 3;
  constant addr_low : integer := 1;

component JTAGController is
  generic (
    base_address      : integer := 0;   -- base address (in bytes)
    address_increment : integer := 2;   -- increment (2 for word access,
                                        -- 4 for long word access)
    addr_high : integer := 3;           -- upper index of vme_addr vector
    addr_low  : integer := 1            -- lower index of vme_addr vector
    );      
                                      
  port (

    -- JTAG port
    -- to be connected directly to I/O pins of chip
    oTck  : out std_logic;              
    oTms0 : out std_logic;
    oTms1 : out std_logic;
    oTdo  : out std_logic;
    iTdi0 : in  std_logic;
    iTdi1 : in  std_logic;

    -- VME port
    vme_addr       : in    std_logic_vector(addr_high downto addr_low);  
                                              
    vme_data       : in    std_logic_vector(15 downto 0);  -- has to be at least 8 bit
    vme_en         : in    std_logic;   -- should not be a pulse when writing
    vme_wr         : in    std_logic;   -- state. must remain for at least two
                                        -- clocks after enable goes to 0
    vme_dtack      : out   std_logic;         -- not inverted

    vme_data_out   : out   std_logic_vector(15 downto 0);
    vme_en_out     : out   std_logic;
        
    -- Clock and control
    clk            : in    std_logic;
    reset          : in    std_logic);  -- asynchronous reset, active high
end component;

--  signal vme_en_jtag : std_logic;
  signal en_tri : std_logic;
  signal tck : std_logic;
  signal tdo : std_logic;
  signal data_jtag : std_logic_vector(15 downto 0);
  signal data_int : std_logic_vector(15 downto 0);
  signal sysres : std_logic;

begin

en_tri <= en_jtag AND NOT write;
data <= data_int(7 downto 0);
data_int <= X"00" & data(7 downto 0);
tck_0 <= tck;
tck_1 <= tck;
tdo_0 <= tdo;
tdo_1 <= tdo;
sysres <= NOT nsysres;

inst_jtag: JTAGController
  generic map(base_address, address_increment, addr_high, addr_low)
  port map(
    oTck => tck,
    oTms0 => tms_0,
    oTms1 => tms_1,
    oTdo => tdo,
    iTdi0 => tdi_0,
    iTdi1 => tdi_1,
    vme_addr => addr,
    vme_data => data_int,
--    vme_en => vme_en_jtag,
    vme_en => en_jtag,
    vme_wr => write,
    vme_dtack => dtack,
    vme_data_out => data_jtag,
    clk => clk,
    reset => sysres
);

tri_loop:
FOR i IN 0 TO 15 GENERATE
  inst_tri: tri
  PORT MAP(data_jtag(i), en_tri, data_int(i));
END GENERATE tri_loop;

end rtl;