--*****************************************************************************
--* @short Combined ROP, VME and JTAG Controller Chip for GMT
--*
--*****************************************************************************
--* @author SAKULIN Hannes <hsakulin@dsy-srv3.cern.ch>
--* @version $Revision: 1.18 $
--* @date $Date: 2006/04/10 09:39:59 $
--*****************************************************************************
--/
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.VMEMux.all;
use work.ROPVMEAddrMap.all;
entity ROPChip is
port (
-- VME port (from/to VME 64 chip)
-- vme addr and data will be buffered to get shorter traces on the board
vme_addr : in std_logic_vector(23 downto 1); -- Bank 7 or 0
vme_data : inout std_logic_vector(15 downto 0); -- Bank 0
-- VME64x chip signals : --- Bank 0
BERR_EXT : out std_logic;
DTACK_EXT : out std_logic;
IRQ_X : out std_logic; -- currently not used
SINGLE_ACCESS : in std_logic; -- address mod indicates single access
BLT_ACCESS : in std_logic; -- address mod indicates block transfer
DSPULS : in std_logic; -- Strobe pulse 25 ns long, 25ns after
-- DSSYNC
DSCYC : in std_logic; -- AND of two VME strobes (not synced)
DSSYNC : in std_logic; -- DSCYC cynchronized
WRITE_I : in std_logic; -- write from VME
RESET_MODE : in std_logic; -- currently not used
D08_O : in std_logic; -- currently not used
D08_E : in std_logic; -- currently not used
D16_EO : in std_logic; -- currently not used
ASCYC : in std_logic; -- currently not used
ASSYNC : in std_logic; -- currently not used
ASPULS : in std_logic; -- currently not used
-- signals from/to Frontpanel -- Bank 1
SET_RUNNING : out std_logic;
VME_LED : out std_logic;
dcm_locked_LED : out std_logic; -- DCM is locked
error_LED : out std_logic;
-- flash a green front panel LED if all FPGA incl. ROP
-- have locked to the external clock
-- VME signals to the other chips (including IRQ, but without BERR)
vme_en_INF : out std_logic; -- Bank 2
vme_wr_INF : out std_logic;
vme_ndtack_INF : in std_logic;
vme_nirq_INF : in std_logic;
vme_en_INC : out std_logic; -- Bank 2
vme_wr_INC : out std_logic;
vme_ndtack_INC : in std_logic;
vme_nirq_INC : in std_logic;
vme_en_IND : out std_logic; -- Bank 3
vme_wr_IND : out std_logic;
vme_ndtack_IND : in std_logic;
vme_nirq_IND : in std_logic;
vme_en_INB : out std_logic; -- Bank 3
vme_wr_INB : out std_logic;
vme_ndtack_INB : in std_logic;
vme_nirq_INB : in std_logic;
vme_en_AUF : out std_logic; -- Bank 2
vme_wr_AUF : out std_logic;
vme_ndtack_AUF : in std_logic;
vme_nirq_AUF : in std_logic;
vme_en_LFF : out std_logic; -- Bank 2
vme_wr_LFF : out std_logic;
vme_ndtack_LFF : in std_logic;
vme_nirq_LFF : in std_logic;
vme_en_LFB : out std_logic; -- Bank 3
vme_wr_LFB : out std_logic;
vme_ndtack_LFB : in std_logic;
vme_nirq_LFB : in std_logic;
vme_en_AUB : out std_logic; -- Bank 3
vme_wr_AUB : out std_logic;
vme_ndtack_AUB : in std_logic;
vme_nirq_AUB : in std_logic;
vme_en_SRT : out std_logic; -- Bank 4 or 5
vme_wr_SRT : out std_logic;
vme_ndtack_SRT : in std_logic;
vme_nirq_SRT : in std_logic;
-- STATUS Signals of FPGAs for VME -- Bank 2 and 3
dcm_locked_INF : in std_logic;
dcm_locked_INC : in std_logic;
dcm_locked_IND : in std_logic;
dcm_locked_INB : in std_logic;
dcm_locked_AUF : in std_logic;
dcm_locked_LFF : in std_logic;
dcm_locked_LFB : in std_logic;
dcm_locked_AUB : in std_logic;
dcm_locked_SRT : in std_logic; -- Bank 4 or 5
-- Dummy signals (as spares)
dummy_INF : out std_logic;
dummy_INC : out std_logic;
dummy_IND : out std_logic;
dummy_INB : out std_logic;
dummy_AUF : out std_logic;
dummy_LFF : out std_logic;
dummy_LFB : out std_logic;
dummy_AUB : out std_logic;
dummy_SRT : out std_logic; -- Bank 4 or 5
-- STATUS Signals of FPGAs for TCS
status_INF : in std_logic_vector(1 downto 0); -- Bank 2
status_INC : in std_logic_vector(1 downto 0); -- Bank 2
status_IND : in std_logic_vector(1 downto 0); -- Bank 3
status_INB : in std_logic_vector(1 downto 0); -- Bank 3
status_AUF : in std_logic_vector(1 downto 0); -- Bank 2
status_LFF : in std_logic_vector(1 downto 0); -- Bank 2
status_LFB : in std_logic_vector(1 downto 0); -- Bank 3
status_AUB : in std_logic_vector(1 downto 0); -- Bank 3
status_SRT : in std_logic_vector(1 downto 0); -- Bank 4 or 5
STAT_GMT : out std_logic_vector(3 downto 0); -- Bank 5 or 6
-- RESET Signals to FPGAs
-- generated either by VME or
-- by Trigger Control: BGo-command ==>TTCrx(TIM)==> RO_BUS(backplane)
-- The reset_ROP will be generated and used inside the ROP chip.
-- ... resets only state machines, FFs,counters, error flags
-- but not memories and registers
reset_INF : out std_logic; -- Bank 2 and 3
reset_INC : out std_logic;
reset_IND : out std_logic;
reset_INB : out std_logic;
reset_AUF : out std_logic;
reset_LFF : out std_logic;
reset_LFB : out std_logic;
reset_AUB : out std_logic;
reset_SRT : out std_logic; -- Bank 4 or 5
reset_dcm_INF : out std_logic;
reset_dcm_INC : out std_logic;
reset_dcm_IND : out std_logic;
reset_dcm_INB : out std_logic;
reset_dcm_AUF : out std_logic;
reset_dcm_LFF : out std_logic;
reset_dcm_LFB : out std_logic;
reset_dcm_AUB : out std_logic;
reset_dcm_SRT : out std_logic;
-- Direct Configuration of FPGA chips via VME - not of Proms
v_nprog_INF : out std_logic; -- normal output -- Bank 2
v_cclk_INF : out std_logic; -- tri state output
v_din_INF : out std_logic; -- tri state output
v_ninit_INF : inout std_logic; -- BIDIRECTIONAL with tristate output
v_done_INF : in std_logic;
v_nprog_INC : out std_logic; -- normal output -- Bank 2
v_cclk_INC : out std_logic; -- tri state output
v_din_INC : out std_logic; -- tri state output
v_ninit_INC : inout std_logic; -- BIDIRECTIONAL with tristate output
v_done_INC : in std_logic;
v_nprog_IND : out std_logic; -- normal output -- Bank 3
v_cclk_IND : out std_logic; -- tri state output
v_din_IND : out std_logic; -- tri state output
v_ninit_IND : inout std_logic; -- BIDIRECTIONAL with tristate output
v_done_IND : in std_logic;
v_nprog_INB : out std_logic; -- normal output -- Bank 3
v_cclk_INB : out std_logic; -- tri state output
v_din_INB : out std_logic; -- tri state output
v_ninit_INB : inout std_logic; -- BIDIRECTIONAL with tristate output
v_done_INB : in std_logic;
v_nprog_AUF : out std_logic; -- normal output -- Bank 2
v_cclk_AUF : out std_logic; -- tri state output
v_din_AUF : out std_logic; -- tri state output
v_ninit_AUF : inout std_logic; -- BIDIRECTIONAL with tristate output
v_done_AUF : in std_logic;
v_nprog_LFF : out std_logic; -- normal output -- Bank 2
v_cclk_LFF : out std_logic; -- tri state output
v_din_LFF : out std_logic; -- tri state output
v_ninit_LFF : inout std_logic; -- BIDIRECTIONAL with tristate output
v_done_LFF : in std_logic;
v_nprog_LFB : out std_logic; -- normal output -- Bank 3
v_cclk_LFB : out std_logic; -- tri state output
v_din_LFB : out std_logic; -- tri state output
v_ninit_LFB : inout std_logic; -- BIDIRECTIONAL with tristate output
v_done_LFB : in std_logic;
v_nprog_AUB : out std_logic; -- normal output -- Bank 3
v_cclk_AUB : out std_logic; -- tri state output
v_din_AUB : out std_logic; -- tri state output
v_ninit_AUB : inout std_logic; -- BIDIRECTIONAL with tristate output
v_done_AUB : in std_logic;
v_nprog_SRT : out std_logic; -- normal output -- Bank 4 or 5
v_cclk_SRT : out std_logic; -- tri state output
v_din_SRT : out std_logic; -- tri state output
v_ninit_SRT : inout std_logic; -- BIDIRECTIONAL with tristate output
v_done_SRT : in std_logic;
-- **** JTAG Chains on GMT board ****
-- CHAIN_1: VME64x and its Proms <== ByteBlaster or Backplane-JTAG
-- CHAIN_2: ROP and its Proms <== ParallelCableIV or Backplane-JTAG
-- CHAIN_3: INB, INC, IND, INF, LFB, LFF, AUB, AUF, SRT and their PROMS
-- controlled by <== VME
-- CHAIN_2 and CHAIN_3 can be combined to one chain using JUMPERS
-- Builtin JTAG Controller I/Os controlled via VME
-- -- Bank 4 or 5
V_TD_VME2GMT : out std_logic; -- goes to TDI of first device in the chain
V_TD_GMT2VME : in std_logic; -- comes from TDO of last device in chain
V_TMS : out std_logic; --
V_TCK : out std_logic;
-- Builtin JTAG Controller I/Os controlled via VME
-- 2nd chain: for altera PROM VME64 chip
-- -- Bank 4 or 5
VA_TD_VME2GMT : out std_logic; -- goes to TDI of first device in the chain
VA_TD_GMT2VME : in std_logic; -- comes from TDO of last device in chain
VA_TMS : out std_logic; --
VA_TCK : out std_logic;
-- JTAG pins of ROP chip (will not be included by Xilinx software)
-- Chain2:
-- TDO_ROP
-- TDI_ROP
-- TMS_ROP
-- TCK_ROP
-- ROP: Readout Data Ports to Input and Sort Chips 130 pins
ro_data_INF : in std_logic_vector(23 downto 0); -- Bank 2
ro_rdfifo_INF : out std_logic;
ro_fetch_INF : out std_logic;
ro_data_INC : in std_logic_vector(23 downto 0); -- Bank 2
ro_rdfifo_INC : out std_logic;
ro_fetch_INC : out std_logic;
ro_data_IND : in std_logic_vector(23 downto 0); -- Bank 3
ro_rdfifo_IND : out std_logic;
ro_fetch_IND : out std_logic;
ro_data_INB : in std_logic_vector(23 downto 0); -- Bank 3
ro_rdfifo_INB : out std_logic;
ro_fetch_INB : out std_logic;
ro_data_SRT : in std_logic_vector(23 downto 0); -- Bank 4 or 5
ro_rdfifo_SRT : out std_logic;
ro_fetch_SRT : out std_logic;
-- Output of ROP to Channel Links with CLK signal
ch_link1 : out std_logic_vector(27 downto 0); -- Bank 6
ch_link1_clk : out std_logic; -- Bank 6
en_link1 : out std_logic;
-- second channel link as spare
ch_link2 : out std_logic_vector(27 downto 0); -- Bank 6
ch_link2_clk : out std_logic; -- Bank 6
en_link2 : out std_logic;
-- BAckplane Timing and Control Signals -- Bank 5
-- L1A, L1reset, bcreset
l1a_ROP : in std_logic; -- Level-1 accept
bcreset_ROP : in std_logic; -- Bunch Counter reset
l1reset_ROP : in std_logic; -- Level-1 reset
-- RO-bus from backplane comes from TTCrx chip on TIM board
-- and carries BGo commands of TTC system
-- Start Stop, HardRes, etc.
-- Can be used to send in addition to VME commands
-- a RESET_xxx to the GMT chips.
ro_bus : in std_logic_vector(11 downto 0); -- Bank 7 or 6
ro_strobe : in std_logic_vector(2 downto 0); -- Bank 7 or 6
ro_rdrqst : in std_logic; -- Bank 7 or 6
-- Clock and control -- at standard positions
clk_ROP : in std_logic;
clk_test_ROP : out std_logic; -- clock1x from DCM
clk_out_ROP : out std_logic; -- clock output for feedback (use optional)
-- same as clk_test
clk_fb_ROP : in std_logic; -- clock feedback input (use optional)
inactive : in std_logic;
dummyb_ROP : out std_logic; -- goes to a Test point on the GMT board
-- Optional Test Pins if possible
test_pins : out std_logic_vector(7 downto 0)); -- Bank 1
end;
architecture behavioral of ROPChip is
attribute syn_useioff : boolean;
attribute syn_useioff of behavioral : architecture is true;
constant date_string : string := "$Date: 2006/04/10 09:39:59 $";
-- registerd board address
signal vme_addr_board_i : std_logic_vector(23 downto 1);
signal sDTACK_EXT : std_logic; -- DTACK signal
signal ds_puls_reg : std_logic; -- registered ds pulse for registering
-- data to JTAG interface
-- signals from / to internal VME interface
signal vme_en_ROP : std_logic;
signal vme_strobe_ROP : std_logic;
signal vme_wr_ROP : std_logic;
signal vme_ndtack_ROP : std_logic;
signal vme_nirq_ROP : std_logic;
-- registered signals from pins or internal VME internal
signal vme_addr_i : std_logic_vector(19 downto 1);
signal vme_data_i : std_logic_vector(15 downto 0);
signal vme_data_to_JTAG : std_logic_vector(15 downto 0);
signal vme_en_i : std_logic;
signal vme_wr_i : std_logic;
signal vme_strobe_i : std_logic;
signal vme_ndtack_default : std_logic;
signal vme_dtack_JTAG : std_logic;
-- VME Mux
signal vme_data_out_i : TVMEData_vec (0 to 6);
signal vme_en_out_i : TVMEEnable_vec (0 to 6);
signal vme_data_out_muxed : std_logic_vector(15 downto 0);
signal vme_en_out : std_logic;
signal dcm_locked_ROP : std_logic;
signal dummy_ROP : std_logic; -- from dummy cmd register not used
signal status_ROP : std_logic_vector(1 downto 0);
signal reset_ROP : std_logic; -- do not use. Makes no sense that ROP
-- resets itself via GSR. The VME cycle
-- would not complete
signal sTdo, sTck : std_logic; -- JTAG signals
-- for DCM
signal reset_dcm_ROP : std_logic;
signal clk : std_logic;
signal reset : std_logic; -- asynchronous reset
-- make signals for test pins
signal svme_en_INF : std_logic;
signal svme_wr_INF : std_logic;
signal svme_ndtack_INF : std_logic;
signal s_ch_link1 : std_logic_vector(27 downto 0);
signal s_ro_fetch_INF : std_logic;
signal sDummy : std_logic_vector (15 downto 0);
signal vme_write_to_all_mask : std_logic_vector(15 downto 0);
signal jtag_enable_vec : std_logic_vector(15 downto 0);
signal sV_TMS : std_logic;
signal sVA_TMS : std_logic;
-- added by Tobias Noebauer:
-- used to send bcreset to ROPBoardControl for forwarding to AUF and AUB
-- chips (for synchronous Mip/Q spy triggering)
signal sBCres : std_logic;
begin
-- added by Tobias Noebauer:
sBCres <= bcreset_ROP;
-----------------------------------------------------------------------------
-- register VME data and addresses
-----------------------------------------------------------------------------
register_vme : process (clk) is
begin -- process register_vme
if clk'event and clk = '1' then -- rising clock edge
vme_addr_board_i <= vme_addr;
end if;
end process register_vme;
-----------------------------------------------------------------------------
--* VME write to all mask register
-----------------------------------------------------------------------------
vmewrite_to_all_mask_reg: entity work.VMEReg
generic map (
init_val => "0000000000011110", -- default: all four input chips
my_vme_base_address => ROP_VMEWriteAllMask_addr)
port map (
data => vme_write_to_all_mask,
vme_addr => vme_addr_i,
vme_data => vme_data_i,
vme_en => vme_en_i,
vme_wr => vme_wr_i,
vme_data_out => vme_data_out_i(5),
vme_en_out => vme_en_out_i(5),
reset => reset,
vme_clk => clk);
-----------------------------------------------------------------------------
--* JTAG enable register (bit 0 for Xilinx JTAG, bit 1 for Altera JTAG)
-----------------------------------------------------------------------------
jtag_enable_reg: entity work.VMEReg
generic map (
init_val => "0000000000000000",
my_vme_base_address => ROP_JTAG_enable_addr)
port map (
data => jtag_enable_vec,
vme_addr => vme_addr_i,
vme_data => vme_data_i,
vme_en => vme_en_i,
vme_wr => vme_wr_i,
vme_data_out => vme_data_out_i(6),
vme_en_out => vme_en_out_i(6),
reset => reset,
vme_clk => clk);
-----------------------------------------------------------------------------
-- VME Interface block
-----------------------------------------------------------------------------
vme_interface : entity work.ROPVMEInterface
port map (
vme_addr => vme_addr_board_i,
vme_wrall_mask => vme_write_to_all_mask(9 downto 0),
BERR_EXT => BERR_EXT,
DTACK_EXT => sDTACK_EXT,
IRQ_X => IRQ_X,
SINGLE_ACCESS => SINGLE_ACCESS,
BLT_ACCESS => BLT_ACCESS,
DSPULS => DSPULS,
DSCYC => DSCYC,
DSSYNC => DSSYNC,
WRITE_I => WRITE_I,
RESET_MODE => RESET_MODE,
D08_O => D08_O,
D08_E => D08_E,
D16_EO => D16_EO,
ASCYC => ASCYC,
ASSYNC => ASSYNC,
ASPULS => ASPULS,
vme_en_INF => svme_en_INF, vme_wr_INF => svme_wr_INF,
vme_en_INC => vme_en_INC, vme_wr_INC => vme_wr_INC,
vme_en_IND => vme_en_IND, vme_wr_IND => vme_wr_IND,
vme_en_INB => vme_en_INB, vme_wr_INB => vme_wr_INB,
vme_en_AUF => vme_en_AUF, vme_wr_AUF => vme_wr_AUF,
vme_en_LFF => vme_en_LFF, vme_wr_LFF => vme_wr_LFF,
vme_en_LFB => vme_en_LFB, vme_wr_LFB => vme_wr_LFB,
vme_en_AUB => vme_en_AUB, vme_wr_AUB => vme_wr_AUB,
vme_en_SRT => vme_en_SRT, vme_wr_SRT => vme_wr_SRT,
vme_en_ROP => vme_en_ROP, vme_wr_ROP => vme_wr_ROP,
vme_ndtack_INF => svme_ndtack_INF, vme_nirq_INF => vme_nirq_INF,
vme_ndtack_INC => vme_ndtack_INC, vme_nirq_INC => vme_nirq_INC,
vme_ndtack_IND => vme_ndtack_IND, vme_nirq_IND => vme_nirq_IND,
vme_ndtack_INB => vme_ndtack_INB, vme_nirq_INB => vme_nirq_INB,
vme_ndtack_AUF => vme_ndtack_AUF, vme_nirq_AUF => vme_nirq_AUF,
vme_ndtack_LFF => vme_ndtack_LFF, vme_nirq_LFF => vme_nirq_LFF,
vme_ndtack_LFB => vme_ndtack_LFB, vme_nirq_LFB => vme_nirq_LFB,
vme_ndtack_AUB => vme_ndtack_AUB, vme_nirq_AUB => vme_nirq_AUB,
vme_ndtack_SRT => vme_ndtack_SRT, vme_nirq_SRT => vme_nirq_SRT,
vme_ndtack_ROP => vme_ndtack_ROP, vme_nirq_ROP => vme_nirq_ROP,
vme_strobe_ROP => vme_strobe_ROP,
clk => clk,
reset => reset);
DTACK_EXT <= sDTACK_EXT;
vme_en_INF <= svme_en_INF;
vme_wr_INF <= svme_wr_INF;
svme_ndtack_INF <= vme_ndtack_INF;
-- assign test pins
test_pins(0) <= svme_en_INF;
test_pins(2) <= svme_wr_INF;
test_pins(4) <= svme_ndtack_INF;
test_pins(6) <= sDTACK_EXT;
test_pins(1) <= s_ch_link1(0);
test_pins(3) <= s_ro_fetch_INF;
test_pins(5) <= '0';
test_pins(7) <= '0';
-----------------------------------------------------------------------------
-- Readout Processor
-----------------------------------------------------------------------------
rop: entity work.ROPROP
port map (
ro_data_INF => ro_data_INF,
ro_rdfifo_INF => ro_rdfifo_INF,
ro_fetch_INF => s_ro_fetch_INF,
ro_data_INC => ro_data_INC,
ro_rdfifo_INC => ro_rdfifo_INC,
ro_fetch_INC => ro_fetch_INC,
ro_data_IND => ro_data_IND,
ro_rdfifo_IND => ro_rdfifo_IND,
ro_fetch_IND => ro_fetch_IND,
ro_data_INB => ro_data_INB,
ro_rdfifo_INB => ro_rdfifo_INB,
ro_fetch_INB => ro_fetch_INB,
ro_data_SRT => ro_data_SRT,
ro_rdfifo_SRT => ro_rdfifo_SRT,
ro_fetch_SRT => ro_fetch_SRT,
ch_link1 => s_ch_link1,
ch_link1_clk => ch_link1_clk,
en_link1 => en_link1,
ch_link2 => ch_link2,
ch_link2_clk => ch_link2_clk,
en_link2 => en_link2,
l1a_ROP => l1a_ROP,
bcreset_ROP => sBCres, -- changed by TN: formerly:
-- bcreset_ROP <= bcres_ROP
l1reset_ROP => l1reset_ROP,
ro_bus => ro_bus,
ro_strobe => ro_strobe,
ro_rdrqst => ro_rdrqst,
vme_addr => vme_addr_i,
vme_data => vme_data_i,
vme_en => vme_en_i,
vme_wr => vme_wr_i,
vme_data_out => vme_data_out_i(0),
vme_en_out => vme_en_out_i(0),
clk => clk,
reset => reset);
-- signals are also connected to test pins
ch_link1 <= s_ch_link1; --apply to output pins
ro_fetch_INF <= s_ro_fetch_INF;
-----------------------------------------------------------------------------
-- Board Control
-----------------------------------------------------------------------------
board_control : entity work.ROPBoardControl
port map (
dcm_locked_ROP => dcm_locked_ROP, dummy_ROP => dummy_ROP, status_ROP => status_ROP,
dcm_locked_INF => dcm_locked_INF, dummy_INF => dummy_INF, status_INF => status_INF,
dcm_locked_INC => dcm_locked_INC, dummy_INC => dummy_INC, status_INC => status_INC,
dcm_locked_IND => dcm_locked_IND, dummy_IND => dummy_IND, status_IND => status_IND,
dcm_locked_INB => dcm_locked_INB, dummy_INB => dummy_INB, status_INB => status_INB,
dcm_locked_AUF => dcm_locked_AUF, dummy_AUF => dummy_AUF, status_AUF => status_AUF,
dcm_locked_LFF => dcm_locked_LFF, dummy_LFF => dummy_LFF, status_LFF => status_LFF,
dcm_locked_LFB => dcm_locked_LFB, dummy_LFB => dummy_LFB, status_LFB => status_LFB,
dcm_locked_AUB => dcm_locked_AUB, dummy_AUB => dummy_AUB, status_AUB => status_AUB,
dcm_locked_SRT => dcm_locked_SRT, dummy_SRT => dummy_SRT, status_SRT => status_SRT,
STAT_GMT => STAT_GMT,
reset_ROP => reset_ROP,
reset_INF => reset_INF, v_nprog_INF => v_nprog_INF, v_cclk_INF => v_cclk_INF,
reset_INC => reset_INC, v_nprog_INC => v_nprog_INC, v_cclk_INC => v_cclk_INC,
reset_IND => reset_IND, v_nprog_IND => v_nprog_IND, v_cclk_IND => v_cclk_IND,
reset_INB => reset_INB, v_nprog_INB => v_nprog_INB, v_cclk_INB => v_cclk_INB,
reset_AUF => reset_AUF, v_nprog_AUF => v_nprog_AUF, v_cclk_AUF => v_cclk_AUF,
reset_LFF => reset_LFF, v_nprog_LFF => v_nprog_LFF, v_cclk_LFF => v_cclk_LFF,
reset_LFB => reset_LFB, v_nprog_LFB => v_nprog_LFB, v_cclk_LFB => v_cclk_LFB,
reset_AUB => reset_AUB, v_nprog_AUB => v_nprog_AUB, v_cclk_AUB => v_cclk_AUB,
reset_SRT => reset_SRT, v_nprog_SRT => v_nprog_SRT, v_cclk_SRT => v_cclk_SRT,
v_din_IND => v_din_IND, v_ninit_IND => v_ninit_IND, v_done_IND => v_done_IND,
v_din_INC => v_din_INC, v_ninit_INC => v_ninit_INC, v_done_INC => v_done_INC,
v_din_INB => v_din_INB, v_ninit_INB => v_ninit_INB, v_done_INB => v_done_INB,
v_din_INF => v_din_INF, v_ninit_INF => v_ninit_INF, v_done_INF => v_done_INF,
v_din_AUF => v_din_AUF, v_ninit_AUF => v_ninit_AUF, v_done_AUF => v_done_AUF,
v_din_LFF => v_din_LFF, v_ninit_LFF => v_ninit_LFF, v_done_LFF => v_done_LFF,
v_din_LFB => v_din_LFB, v_ninit_LFB => v_ninit_LFB, v_done_LFB => v_done_LFB,
v_din_AUB => v_din_AUB, v_ninit_AUB => v_ninit_AUB, v_done_AUB => v_done_AUB,
v_din_SRT => v_din_SRT, v_ninit_SRT => v_ninit_SRT, v_done_SRT => v_done_SRT,
reset_dcm_INF => reset_dcm_INF,
reset_dcm_INC => reset_dcm_INC,
reset_dcm_IND => reset_dcm_IND,
reset_dcm_INB => reset_dcm_INB,
reset_dcm_AUF => reset_dcm_AUF,
reset_dcm_LFF => reset_dcm_LFF,
reset_dcm_LFB => reset_dcm_LFB,
reset_dcm_AUB => reset_dcm_AUB,
reset_dcm_SRT => reset_dcm_SRT,
vme_addr => vme_addr_i,
vme_data => vme_data_i,
vme_en => vme_en_i,
vme_wr => vme_wr_i,
vme_data_out => vme_data_out_i(1),
vme_en_out => vme_en_out_i(1),
clk => clk,
reset => reset,
BCres => sBCres -- added by TN
);
-----------------------------------------------------------------------------
-- JTAG Controller
-----------------------------------------------------------------------------
jtag_controller : entity work.JTAGController
generic map (
base_address => ROP_JTAG_base,
address_increment => 2,
addr_high => 19,
addr_low => 1)
port map (
oTck => sTck,
oTms0 => sV_TMS,
oTms1 => sVA_TMS,
oTdo => sTdo,
iTdi0 => V_TD_GMT2VME,
iTdi1 => VA_TD_GMT2VME,
vme_addr => vme_addr_i,
vme_data => vme_data_to_JTAG,
vme_en => vme_strobe_i,
vme_wr => vme_wr_i,
vme_dtack => vme_dtack_JTAG,
vme_data_out => vme_data_out_i(2),
vme_en_out => vme_en_out_i(2),
clk => clk,
reset => reset);
V_TD_VME2GMT <= sTdo when jtag_enable_vec(0)='1' else 'Z';
V_TMS <= sV_TMS when jtag_enable_vec(0)='1' else 'Z';
V_TCK <= sTck when jtag_enable_vec(0)='1' else 'Z';
VA_TD_VME2GMT <= sTdo when jtag_enable_vec(1)='1' else 'Z';
VA_TMS <= sVA_TMS when jtag_enable_vec(1)='1' else 'Z';
VA_TCK <= sTck when jtag_enable_vec(1)='1' else 'Z';
-----------------------------------------------------------------------------
-- Chip ID and Revision
-----------------------------------------------------------------------------
ChipID: entity work.ChipIDRegisters
generic map (
idregisters_vme_base_address => ROP_chip_id0_raddr,
chipID_h => 16#0001#, chipID_l => 16#9121#,
chipRev_h => 16#DEAD#, chipRev_l => 16#0002#, --increased by TN
--20.02.06 (BCres to AUF/AUB)
date_string => date_string)
port map (
vme_addr => vme_addr_i,
vme_en => vme_en_i,
vme_wr => vme_wr_i,
vme_data_out => vme_data_out_i(3),
vme_en_out => vme_en_out_i(3),
vme_clk => clk,
reset => reset);
-----------------------------------------------------------------------------
-- Dummy signals
-----------------------------------------------------------------------------
sDummy(0) <=
clk_fb_ROP or
-- currently unused VME64 pins
RESET_MODE or
D08_O or
D08_E or
D16_EO or
ASCYC or
ASSYNC or
ASPULS or
clk_fb_ROP;
sDummy(15 downto 1) <= (others => '0');
-----------------------------------------------------------------------------
--* Dummy register
-----------------------------------------------------------------------------
dummy_reg: entity work.VMEStatusReg
generic map (
my_vme_base_address => ROP_dummy_raddr)
port map (
data => sDummy,
vme_addr => vme_addr_i,
vme_en => vme_en_i,
vme_wr => vme_wr_i,
vme_data_out => vme_data_out_i(4),
vme_en_out => vme_en_out_i(4),
vme_clk => clk,
reset => reset);
-----------------------------------------------------------------------------
-- VME Logic (use the same as for the other chip)
--
-- but do not use it for the JTAG controller which does its own DTACK
-----------------------------------------------------------------------------
-- multiplex vme_data_output
mux_vme(vme_data_out_i, vme_en_out_i, vme_data_out_muxed, vme_en_out);
vme_logic: entity work.InChipVMELogic
port map (
vme_addr => vme_addr(19 downto 1), -- from chip pin
vme_data => vme_data, -- from chip pin
vme_en => vme_en_ROP, -- from VMEInterface in chip
vme_wr => vme_wr_ROP, -- from VMEInterface in chip
vme_ndtack => vme_ndtack_default,
vme_nirq => vme_nirq_ROP, -- to VMEInterface in chip
vme_addr_i => vme_addr_i, -- to regs in chip
vme_data_i => vme_data_i, -- to regs in chip
vme_en_i => vme_en_i, -- to regs in chip
vme_wr_i => vme_wr_i, -- to regs in chip
vme_data_out => vme_data_out_muxed, -- from regs and JTAG controller in
-- chip
vme_en_out => vme_en_out, -- from chips and JTGA Contoller
clk => clk,
reset => reset);
--* register vme data to JTAG interface
register_data_to_JTAG: process (clk, reset) is
begin
if reset = '1' then
vme_data_to_JTAG <= (others => '0');
ds_puls_reg <= '0';
elsif clk'event and clk = '1' then
ds_puls_reg <= DSPULS;
if ds_puls_reg = '1' then
vme_data_to_JTAG <= vme_data_i;
end if;
end if;
end process register_data_to_JTAG;
-- delay strobe from ROPVMEInterface to JTAGController
delay_strobe: process (clk, reset) is
begin -- process delay_strobe
if reset = '1' then
vme_strobe_i <= '0';
elsif clk'event and clk = '1' then
vme_strobe_i <= vme_strobe_ROP;
end if;
end process delay_strobe;
-- combine DTACK from VME Logic (used for registers)
-- and from JTAG controller: use the standard DTACK, when the normal
-- registers are selected, otherwise use the JTAG DTACK
vme_ndtack_ROP <= not (
( (not vme_ndtack_default) and ( not vme_en_out_i(2)) )
or vme_dtack_JTAG
);
-----------------------------------------------------------------------------
-- Front panel LEDs
-----------------------------------------------------------------------------
vme_led_pulser: entity work.LEDPulser
generic map (
length_in_clocks => 4000000)
port map (
iSignal => sDTACK_EXT,
oLEDPulse => VME_LED,
clk => clk);
dcm_locked_LED <=
dcm_locked_INF and
dcm_locked_INC and
dcm_locked_IND and
dcm_locked_INB and
dcm_locked_AUF and
dcm_locked_LFF and
dcm_locked_LFB and
dcm_locked_AUB and
dcm_locked_SRT and
dcm_locked_ROP;
-------------------------------------------------------------------------------
-- Digital Clock Management & Chip Startup
-------------------------------------------------------------------------------
reset_dcm_ROP <= '0';
startup_dcm: entity work.StartupDCMVirtex2
port map (
iResetToGSR => reset_ROP,
iTristateToGTS => inactive,
oResetNet => reset,
iClkFromPAD => clk_ROP,
oClkNet => clk,
iResetDCM => reset_dcm_ROP,
oDCMLocked => dcm_locked_ROP);
clk_out_ROP <= clk;
clk_test_ROP <= clk;
-----------------------------------------------------------------------------
-- Status handling
-----------------------------------------------------------------------------
status_ROP <= "00"; -- FIXME: add some status
SET_RUNNING <= '0';
error_LED <= '0';
-- flash a green front panel LED if all FPGA incl. ROP
-- have locked to the external clock
-- dummy output
dummyb_ROP <= '0';
end architecture behavioral;