--******************************************************************************
--* @short   A VME register that generates a programming pulse upon write
--*          Used for FPGA configuration.
--*
--******************************************************************************
--* @author  SAKULIN Hannes  <hsakulin@dsy-srv3.cern.ch>
--* @version $Revision: 1.3 $
--* @date    $Date: 2004/12/16 19:03:28 $
--******************************************************************************
--/
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
 

entity ROPProgPulseRegister is
  
  generic (
    address : integer);
  port (
    vme_addr  : in std_logic_vector;  
    vme_data0 : in std_logic;         
    vme_en    : in std_logic;         
    vme_wr    : in std_logic;
    enable    : in std_logic;
    clk       : in std_logic;         
                                      
    din       : out std_logic;        
    cclk      : out std_logic);
end entity ROPProgPulseRegister;


architecture behavioral of ROPProgPulseRegister is
  attribute syn_useioff               : boolean;
  attribute syn_useioff of behavioral : architecture is true;

  function addr_match (
    constant vme_addr : std_logic_vector;
    constant address  : integer)        -- in bytes
    return boolean is

    variable my_addr_vec : std_logic_vector(vme_addr'high downto 0);
  begin  -- process vme_addr_decode
    my_addr_vec := std_logic_vector( TO_UNSIGNED ( address, vme_addr'high+1 ) );
    return my_addr_vec(vme_addr'high downto 1) = vme_addr(vme_addr'high downto 1);
  end;

begin  -- architecture behavioral
    -- needs enable pulse 
    program_pulse: process (clk) is
    begin  
      if clk'event and clk = '1' then  -- rising clock edge
        if (enable = '0') then
          din  <= 'Z';
          cclk <= 'Z';
        else
          if (vme_en = '1' and vme_wr = '1' and addr_match(vme_addr, address)) then
            din  <= vme_data0;
            cclk <= '1';
          else
            cclk <= '0';
          end if;      
        end if;
      end if;
    end process program_pulse;
end architecture behavioral;