-------------------------------------------------------------------------------
-- Title      : DelayLine_pm.vhd
-- Project    : 
-------------------------------------------------------------------------------
-- File       : DelayLine_pm.vhd
-- Author     : SAKULIN Hannes  <hsakulin@dsy-srv1.cern.ch>
-- Company    : 
-- Platform   : 
-------------------------------------------------------------------------------
-- Description: Delay by n half-cycles
-------------------------------------------------------------------------------
-- $Revision: 1.1 $
-- $Date: 2003/07/24 13:20:54 $
-------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.GMTTypes.all;

entity DelayLine_pm is
  
  generic (
    n_halfcycles : integer := 2);

  port (
    x         : in TPairMatrix;
    x_delayed : out TPairMatrix;
    clk       : in std_logic);

end entity DelayLine_pm;


architecture xx of DelayLine_pm is
  type TBuf is array (integer range <>) of TPairMatrix;
  signal buf : TBuf(0 to n_halfcycles);

begin  -- architecture xx

  
  shift: process (clk) is
  begin  -- process shift
    if clk'event then 
      for i in 0 to n_halfcycles-2 loop
        buf(i) <= buf(i+1);
      end loop;  -- i
      x_delayed <= buf(0);
      buf(n_halfcycles-1) <= x;
    end if;
  end process shift;

end architecture xx;