-------------------------------------------------------------------------------
-- Title      : DelayLine.vhd
-- Project    : 
-------------------------------------------------------------------------------
-- File       : DelayLine.vhd
-- Author     : SAKULIN Hannes  <hsakulin@dsy-srv1.cern.ch>
-- Company    : 
-- Platform   : 
-------------------------------------------------------------------------------
-- Description: Delay by n half-cycles
-------------------------------------------------------------------------------
-- $Revision: 1.2 $
-- $Date: 2003/11/14 16:32:38 $
-------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.NUMERIC_STD.all;

entity DelayLine is
  
  generic (
    n_halfcycles : integer := 2);

  port (
    x         : in std_logic_vector;
    x_delayed : out std_logic_vector;
    clk       : in std_logic);

end entity DelayLine;


architecture xx of DelayLine is
  type TBuf is array (integer range <>) of std_logic_vector(x'range);
  signal buf : TBuf(0 to n_halfcycles-2);

begin  -- architecture xx
  assert n_halfcycles>=2 report "DelayLine: n_halfcycles has to be graeter than or equal to 2" severity failure;
  
  shift: process (clk) is
  begin  -- process shift
    if clk'event then 
      for i in 0 to n_halfcycles-3 loop
        buf(i) <= buf(i+1);
      end loop;  -- i
      x_delayed <= buf(0);
      buf(n_halfcycles-2) <= x;
    end if;
  end process shift;

end architecture xx;