|
Annotated List |
| BUFG_CLK0_SUBM | BUFG_CLK0_SUBM VHDL submodule. |
| BUFG_DCM_80 | BUFG_DCM_80 VHDL submodule. |
| BXCounter | 12 bit BX counter with delay for bx reset configurable by VME. |
| BXReadCounter | 12 bit BX counter used for the read address in the FIFOs of the Input Chips and Sort Chip. Also used as reference bunch counter in the ROP chip. |
| ChipIDRegisters | Block of CHIP ID and revision / date registers. |
| DelayLine | |
| DelayLine_pm | |
| ErrorCounter | 12-bit Error counter: counts errors and can be read out via VME. |
| ErrorCounter16bit | 16-bit Error counter: counts errors and can be read out via VME. |
| ErrorCounterVec | Vector of 16-bit Error counters: counts errors and can be read out via VME. |
| ErrorMonitor4x4bit | Error Monitor for 4 x 4 bits. |
| GMTBoard_tb | |
| InChipVMELogic | The InChip VME Logic. |
| InputFPGA | Input FPGA: synchronizes 4 muons. |
| InputFPGAbrpc | Input FPGA (BRPC version). |
| InputFPGAcsc | Input FPGA (CSC version). |
| InputFPGAdt | Input FPGA (DT version). |
| InputFPGAfrpc | Input FPGA (FRPC version). |
| JTAGController | Simplified version of a ScanPSC100 JTAG controller (by J. Ero). |
| LEDPulser | Block that generates a pulse (used for steering a front panel LED) upon rising edge of a signal. |
| LFCancelOutUnit | Cancel-Out Unit in Logic FPGA. |
| LFConversionUnit | Conversion Unit. Converts the DT/CSC and RPC muons into GMT format. |
| LFDeltaPhiSub | Delta Phi Subtractor (signed, modulo 144). |
| LFMatchingUnit | Matching Unit in Logic FPGA. |
| LFMergeMethodSelector | Merge method selector. Selects merge method for each parameter. |
| LFMergeRankAU | Merge Rank Assignment Unit (for one muon). |
| LFMuonMerger | Muon Merger. Merges the RPC and DT/CSC muons. |
| LFMuonMergerUnit | Muon Merger Unit. merges the one DTCSC/RPC pair. |
| LFOvlDisableHotUnit | Calculate disable hot bits from phi and eta of the DT/CSC muons from the other chip/chain. |
| LFPairLogic | Pair Logic for matching units. |
| LFPhiProUnit | Phi projection unit. Projects phi from muon system to vertex. |
| LFRankAssUnit | Sort Rank Assignment Unit (for one muon). |
| LFSortRankMergeUnit | Sort Rank Merge Unit. merges the sort ranks for one DTCSC/merged moun. |
| LFSortRankMerger | Sort Rank Merger. merges the sort ranks. |
| LFSortRankUnit | Sort Rank Unit. Assigns sort ranks to all input muons. |
| LFSortStage1 | 8->4 Sorter based on sort ranks. |
| LogicFPGA | Logic FPGA (the whole chip). |
| LogicFPGAbrlchip | Logic FPGA (the whole chip) barrel version. |
| LogicFPGAfwdchip | Logic FPGA (the whole chip) forward version. |
| MIAUMQReceiver | MIP and Quiet Bit Receiver. |
| MIAUPhiProUnit | Phi Projection Unit in MIAU Chip (for 1 muon). |
| MIAUSimuLogic | Simulation Logic in the MipIsoAU Chip. |
| MIAUSingleAssUnit | Single Assignment Unit (for 1 muon) in MIAU Chip. |
| MipIsoAU | Mip And Iso Assignment Unit (the whole chip). |
| MipIsoAUbrl | Mip And Iso Assignment Unit (Barrel version). |
| MipIsoAUbrlchip | Mip And Iso Assignment Unit (Barrel Chip). |
| MipIsoAUfwd | Mip And Iso Assignment Unit (Forward version). |
| MipIsoAUfwdchip | Mip And Iso Assignment Unit Forward Chip. |
| PhaseMonitor | Phase monitor: monitors at what phase the input changes for all 4 muons. |
| ROPBlock32 | A 32bit block in the readout unit. |
| ROPBoardControl | Board Control Logic for GMT Logic Board. (Inside ROP Chip). |
| ROPChip | Combined ROP, VME and JTAG Controller Chip for GMT. |
| ROPCombineStatus | Logic to combine the status bits of all chips to the GMT status. (Inside ROP Chip). |
| ROPProgPulseRegister | A VME register that generates a programming pulse upon write Used for FPGA configuration. |
| ROPROP | Readout Processor Module, in the ROP Chip, reads data from the input chips and sort chip. Sends it to GTFE via channel link. |
| ROPVMEInterface | VME Interface Block for the whole GMT Board. Located in the ROP Chip. |
| ReadOutLogic | Readout logic that goes into the Input or Sort FPGA. |
| SFDDROutput | Double Data Rate Output Block. |
| SFDOutput | Data Output Block. |
| SFSortStage2 | 8->4 Sorter based on sort ranks. |
| SimuSpyControlLogic | Control Logic for Simulation And Spy Logic. |
| SimuSpyLogic | Simulation and Spy Logic that goes into the Input or Sort FPGA. |
| SortFPGA | Sort FPGA (there is only one, so this is the chip). |
| StartupDCM80Virtex2 | Startup block and DCM with 80MHz clock for Virtex2. |
| StartupDCMVirtex2 | Startup block and DCM for Virtex2. |
| TCSCommandDecoder | Decoder for the TCS Commands. |
| VMEReadOnlyReg | 16 bit VME read-only register. |
| VMEReg | 16 bit VME register. |
| VMEStatusReg | 16 bit VME status register (read only). |
| VMEWritePulseReg | 16 bit VME Write Pulse register generates 25 ns pulses when written to. |
| bc_l1a_fifo1k | |
| block1k | |
| comp5 | |
| comp6 | |
| comp8 | |
| dcm4x | |
| fifo1kx32 | |
| jtag_ctrl | |
| lfcoudeltaeta_cscbrpc | |
| lfcoudeltaeta_cscdt | |
| lfcoudeltaeta_dtcsc | |
| lfcoudeltaeta_dtfrpc | |
| lfcoudeltaetalut | |
| lfdeltaeta_cscrpc | |
| lfdeltaeta_dtrpc | |
| lfdeltaetalut | |
| lfdisablehot_csc | |
| lfdisablehot_dt | |
| lfdisablehotlut | |
| lfetaconv_brpc | |
| lfetaconv_csc | |
| lfetaconv_dt | |
| lfetaconv_frpc | |
| lfetaconvlut | |
| lfmatchqual_cscbrpc | |
| lfmatchqual_cscdt | |
| lfmatchqual_cscrpc | |
| lfmatchqual_dtcsc | |
| lfmatchqual_dtfrpc | |
| lfmatchqual_dtrpc | |
| lfmatchquallut | |
| lfmergerankcombine_brpc | |
| lfmergerankcombine_csc | |
| lfmergerankcombine_dt | |
| lfmergerankcombine_frpc | |
| lfmergerankcombinelut | |
| lfmergeranketaphi_brpc | |
| lfmergeranketaphi_csc | |
| lfmergeranketaphi_dt | |
| lfmergeranketaphi_frpc | |
| lfmergeranketaphilut | |
| lfmergeranketaq_brpc | |
| lfmergeranketaq_csc | |
| lfmergeranketaq_dt | |
| lfmergeranketaq_frpc | |
| lfmergeranketaqlut | |
| lfmergerankptq_brpc | |
| lfmergerankptq_csc | |
| lfmergerankptq_dt | |
| lfmergerankptq_frpc | |
| lfmergerankptqlut | |
| lfovletaconv_brpc | |
| lfovletaconv_csc | |
| lfovletaconv_dt | |
| lfovletaconv_frpc | |
| lfovletaconv_ovlcsc | |
| lfovletaconv_ovldt | |
| lfovletaconvlut | |
| lfphipro_brpc | |
| lfphipro_csc | |
| lfphipro_dt | |
| lfphipro_frpc | |
| lfphiproetaconv_brpc | |
| lfphiproetaconv_csc | |
| lfphiproetaconv_dt | |
| lfphiproetaconv_frpc | |
| lfphiproetaconvlut | |
| lfphiprolut | |
| lfptmix_cscrpc | |
| lfptmix_dtrpc | |
| lfptmixlut | |
| lfsortrankcombine_brpc | |
| lfsortrankcombine_csc | |
| lfsortrankcombine_dt | |
| lfsortrankcombine_frpc | |
| lfsortrankcombinelut | |
| lfsortranketaphi_brpc | |
| lfsortranketaphi_csc | |
| lfsortranketaphi_dt | |
| lfsortranketaphi_frpc | |
| lfsortranketaphilut | |
| lfsortranketaq_brpc | |
| lfsortranketaq_csc | |
| lfsortranketaq_dt | |
| lfsortranketaq_frpc | |
| lfsortranketaqlut | |
| lfsortrankptq_brpc | |
| lfsortrankptq_csc | |
| lfsortrankptq_dt | |
| lfsortrankptq_frpc | |
| lfsortrankptqlut | |
| miauetaconv_iso_brpc | |
| miauetaconv_iso_csc | |
| miauetaconv_iso_dt | |
| miauetaconv_iso_frpc | |
| miauetaconv_mip_brpc | |
| miauetaconv_mip_csc | |
| miauetaconv_mip_dt | |
| miauetaconv_mip_frpc | |
| miauetaconvlut | |
| miauetapro_iso_brpc | |
| miauetapro_iso_csc | |
| miauetapro_iso_dt | |
| miauetapro_iso_frpc | |
| miauetapro_mip_brpc | |
| miauetapro_mip_csc | |
| miauetapro_mip_dt | |
| miauetapro_mip_frpc | |
| miauetaprolut | |
| miauphipro1_iso_brpc | |
| miauphipro1_iso_csc | |
| miauphipro1_iso_dt | |
| miauphipro1_iso_frpc | |
| miauphipro1_mip_brpc | |
| miauphipro1_mip_csc | |
| miauphipro1_mip_dt | |
| miauphipro1_mip_frpc | |
| miauphipro1lut | |
| miauphipro2_iso_brpc | |
| miauphipro2_iso_csc | |
| miauphipro2_iso_dt | |
| miauphipro2_iso_frpc | |
| miauphipro2_mip_brpc | |
| miauphipro2_mip_csc | |
| miauphipro2_mip_dt | |
| miauphipro2_mip_frpc | |
| miauphipro2lut | |
| ringbuf512x32 | |
| simuspy1k | |
| simuspy4k |
| Generated by: taurokc@dsy-srv3 on Fri Aug 25 11:56:55 2006. |