Index
Annotated List
Hierarchy
Deep Hierarchy
Package Documentation
Files
entity lfmergeranketaphilut
More...
Sourcefile...
Used Packages
IEEE.Std_logic_1164
all
IEEE.Numeric_Std
all
Generics
instance_idx
integer := 0
my_vme_base_address
integer := 0
edge
std_logic := '1'
Ports
eta
in std_logic_vector(5 downto 0)
phi
in std_logic_vector(7 downto 0)
rank_etaphi
out std_logic_vector(0 downto 0)
clk
in std_logic
sinit
in std_logic
vme_addr
in std_logic_vector
vme_data
in std_logic_vector
vme_en
in std_logic
vme_wr
in std_logic
vme_data_out
out std_logic_vector
vme_en_out
out std_logic
vme_clk
in std_logic
Architectures
behavioral
Generated by: taurokc@dsy-srv3 on Fri Aug 25 11:56:55 2006.