entity miauphipro1lut

Used Packages

• IEEE.Std_logic_1164 all
• IEEE.Numeric_Std all

Generics

• instance_idx integer := 0
• my_vme_base_address integer := 0
• edge std_logic := '1'

Ports

• phi_fine in std_logic_vector(2 downto 0)
• eta in std_logic_vector(3 downto 0)
• pt in std_logic_vector(4 downto 0)
• charge in std_logic_vector(0 downto 0)
• cphi_fine out std_logic_vector(0 downto 0)
• cphi_ofs out std_logic_vector(2 downto 0)
• clk in std_logic
• sinit in std_logic
• vme_addr in std_logic_vector
• vme_data in std_logic_vector
• vme_en in std_logic
• vme_wr in std_logic
• vme_data_out out std_logic_vector
• vme_en_out out std_logic
• vme_clk in std_logic

Architectures

• behavioral