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PSB Card

Pipeline Synchronize Buffer Card

• 8 Serial Receivers DS92LV16: 1.2 Gbps 80MHz/16bits
• LVDS Receiver: 64 bits / 40 MHz
• PHASE synchronization: oversampling of parallel input signals
• BC-synchronization: delay circuits for trigger data
• Synchronization to LHC orbit: SIM/SPY memories for each channel
• DAQ: Ringbuffer + FIFO + ROP(state machine)

PSB Module

PSB Schematics

Technical Trigger Input RJ45

Jumper Settings

JTAG Chains

CAD TopView

CAD BottomView

PSB_opt_status_sept08

Last modified by Anton Taurok on Jan,16^th 2009